74HCT40105DB,118 NXP Semiconductors, 74HCT40105DB,118 Datasheet - Page 17

IC FIFO REGISTER 4X16 16SSOP

74HCT40105DB,118

Manufacturer Part Number
74HCT40105DB,118
Description
IC FIFO REGISTER 4X16 16SSOP
Manufacturer
NXP Semiconductors
Series
74HCTr
Datasheet

Specifications of 74HCT40105DB,118

Function
Asynchronous
Memory Size
64 (4 x 16)
Data Rate
25MHz
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Package / Case
16-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Access Time
-
Other names
74HCT40105DB-T
74HCT40105DB-T
935189960118
Philips Semiconductors
Expanded format
Fig.19 shows two cascaded FIFOs providing a capacity of 32 words
Fig.20 shows the signals on the nodes of both FIFOs after the application of a SI pulse, when both FIFOs are initially
empty. After a rippled through delay, date arrives at the output of FIFO
generated. The requirements of SI
edge of DOR
Fig.21 shows the signals on the nodes of both FIFOs after the application of a SO
full. After a bubble-up delay a DIR
from the output of FIFO
width of DOR
Fig.22 shows the waveforms at all external nodes of both FIFOs during a complete shift-in and shift-out sequence.
1998 Jan 23
4-bit x 16-word FIFO register
The PC7HC/HCT40105 is easily cascaded to increase word capacity without any external circuitry. In cascaded format, all necessary
communications are handled by the FIFOs. Figs 17 and 19 demonstrate the intercommunication timing between FIFO
overview of pulse and timing of two cascaded FIFOs, when shifted full and shifted empty again.
A
B
. After a second bubble-up delay an empty space arrives at D
and Q
nA
. After a second ripple through delay, data arrives at the output of FIFO
A
to the input of FIFO
Fig.19 Cascading for increased word capacity; 32 words
R
B
pulse is generated, which acts as a SO
and D
nB
B
are satisfied by the DOR
. The requirements of the SO
17
A
4 bits
A
pulse width and the timing between the rising
. Due to SO
A
A
nA
pulse for FIFO
pulse for FIFO
, at which time DIR
R
pulse, when both FIFOs are initially
A
being HIGH, a DOR pulse is
4 bits.
74HC/HCT40105
A
A
A
. One word is transferred
and FIFO
is satisfied by the pulse
B
.
A
Product specification
goes HIGH.
B
. Fig.22 gives an

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