K20P104M100SF2 Freescale Semiconductor, K20P104M100SF2 Datasheet - Page 24

• Manufacturer Part Number: K20P104M100SF2
• Description: K20 Sub-Family
• Manufacturer: Freescale Semiconductor

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Peripheral operating requirements and behaviors
1. The resulting system clock frequencies should not exceed their maximum specified values.
24
f
dco_t_DMX3
t
Symbol
f
fll_acquire
J
J
f
t
loc_high
J
J
f
t
loc_low
f
pll_lock
D
acc_pll
pll_ref
cyc_pll
D
irefstf
dco_t
cyc_fll
acc_fll
f
vco
lock
2
unl
Internal reference startup time (fast clock)
Loss of external clock minimum frequency —
RANGE = 00
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
DCO output fre‐
quency range —
user trimmed
and DMX32=0
DCO output fre‐
quency range —
reference =
32,768Hz and
DMX32=1
FLL period jitter
FLL accumulated jitter of DCO output over a 1µs
time window
FLL target frequency acquisition time
VCO operating frequency
PLL reference frequency range
PLL period jitter
PLL accumulated jitter over 1µs window
Lock entry frequency tolerance
Lock exit frequency tolerance
Lock detector detection time
Description
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Table 12. MCG specifications (continued)
Mid-high range (DRS=10)
Mid-high range (DRS=10
High range (DRS=11)
High range (DRS=11)
Low range (DRS=00)
Low range (DRS=00)
Mid range (DRS=01)
Mid range (DRS=01)
192)0 × f
1280 × f
2560 × f
1464 × f
2197 × f
2929 × f
640 × f
732 × f
ints_t
ints_t
ints_t
ints_t
ints_t
ints_t
ints_t
ints_t
Preliminary
PLL
FLL
(16/5) x
(3/5) x
± 1.49
± 4.47
f
f
48.0
Min.
ints_t
ints_t
2.0
20
40
60
80
—
—
—
—
—
—
—
—
—
—
—
20.97
41.94
62.91
83.89
23.99
47.97
71.99
95.98
TBD
TBD
TBD
TBD
Typ.
400
—
—
—
—
—
—
—
—
1075(1/
± 2.98
± 5.97
0.15 +
f
Max.
TBD
TBD
TBD
pll_ref
100
100
4.0
25
50
75
—
—
—
—
—
—
—
—
1
Freescale Semiconductor, Inc.
)
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
kHz
kHz
ms
ms
µs
ps
ps
ps
ps
%
%
Notes
6
1,
6,
3
4
5
8
,
2
7
7
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