K20P104M100SF2 Freescale Semiconductor, K20P104M100SF2 Datasheet - Page 51

• Manufacturer Part Number: K20P104M100SF2
• Description: K20 Sub-Family
• Manufacturer: Freescale Semiconductor

www.DataSheet.co.kr
6.8.7 I
This section provides the AC timings for the I
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all
the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame sync
(I2S_FS) shown in the figures below.
Freescale Semiconductor, Inc.
Num
SD6
SD7
SD8
Num
S1
S2
S3
S4
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
Input SDHC_DAT[3:0]
2
S Switching Specifications
Operating voltage
I2S_MCLK cycle time
I2S_MCLK pulse width high/low
I2S_BCLK cycle time
I2S_BCLK pulse width high/low
Description
Symbol
t
t
t
THL
THL
OD
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
Table 40. SDHC switching specifications (continued)
SDHC output delay (output valid)
SDHC input setup time
SDHC input hold time
Description
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Table 41. I
SD3
SD6
Table continues on the next page...
Figure 21. SDHC timing
SD2
SD7
2
S master mode timing
Preliminary
2
SD8
S in master (clocks driven) and slave
SD1
Peripheral operating requirements and behaviors
2 x t
5 x t
45%
45%
Min.
2.7
SYS
SYS
Min.
-5
5
0
Max.
55%
55%
3.6
—
Max.
6.5
—
—
MCLK period
BCLK period
Unit
ns
ns
Unit
V
ns
ns
ns
51
Datasheet pdf - http://www.DataSheet4U.net/