K20P104M100SF2 Freescale Semiconductor, K20P104M100SF2 Datasheet - Page 40

• Manufacturer Part Number: K20P104M100SF2
• Description: K20 Sub-Family
• Manufacturer: Freescale Semiconductor

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Peripheral operating requirements and behaviors
1. Typical values assume V
2. Gain = 2
3. When the PGA gain is changed, it takes some time to settle the output for the ADC to work properly. During a gain
4. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
40
V
Symbol
SINAD
ENOB
SFDR
switching, a few ADC outputs should be discarded (minimum two data samples, may be more depending on ADC
sampling rate and time of the switching).
PGA reference voltage and gain setting.
PP,DIFF
SNR
THD
E
IL
PGAGx
Input leakage er‐
ror
Maximum differ‐
ential input signal
swing
Signal-to-noise
ratio
Total harmonic
distortion
Spurious free dy‐
namic range
Effective number
of bits
Signal-to-noise
plus distortion ra‐
tio
Description
Table 26. 16-bit ADC with PGA characteristics (continued)
DDA
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
=3.0V, Temp=25°C, f
All modes
See ENOB
Conditions
• Gain=1
• Gain=64
• Gain=1
• Gain=64
• Gain=1
• Gain=64
• Gain=1, Average=4
• Gain=1, Average=8
• Gain=64, Average=4
• Gain=64, Average=8
• Gain=1, Average=32
• Gain=2, Average=32
• Gain=4, Average=32
• Gain=8, Average=32
• Gain=16, Average=32
• Gain=32, Average=32
• Gain=64, Average=32
ADCK
Preliminary
=6MHz unless otherwise stated.
[(V
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Min.
REFPGA
6.02 × ENOB + 1.76
I
× 2.33) - 0.2] / (2 ×
In
92.42
92.54
Gain)
Typ.
57.7
87.3
85.3
12.3
12.7
13.4
13.1
12.6
11.8
11.1
10.2
× R
8.3
8.4
8.7
9.3
1
AS
Max.
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Freescale Semiconductor, Inc.
Unit
mV
bits
bits
bits
bits
bits
bits
bits
bits
bits
bits
bits
dB
dB
dB
dB
dB
dB
dB
V
and current op‐
erating ratings)
MCU's voltage
Average=32,
Average=32,
I
Average=32
(refer to the
In
f
f
in
in
= leakage
current
Notes
=100Hz
=100Hz
4
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