LM1229YA National Semiconductor, LM1229YA Datasheet

LM1229YA

Manufacturer Part Number

LM1229YA

Description

I2C Compatible CMOS TV RGB and Deflection Processor

Manufacturer

National Semiconductor

Datasheet

1.LM1229YA.pdf (27 pages)

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LM1229

General Description

The LM1229 pre-amp is an integrated CMOS CRT RGB

preamp plus horizontal and vertical deflection processing

with an I

eters necessary to directly adjust the gain, contrast and

brightness and geometry of the CRT display.

In the RGB section, the CRT bias is controlled by the three

DAC outputs which are matched to the LM248x integrated

bias clamp ICs. The brightness control operates on the video

channels rather than the bias channels and is designed to

maintain the CRT color temperature through the full range of

adjustment. The On Screen Display inputs accept either

digital or analog input levels. Black level clamping of the

video signal is carried out directly on the AC coupled input

signal into the high impedance preamplifier input, thus elimi-

nating the need for additional clamp capacitors. Blanking

inputs are provided which can accept both horizontal and

vertical flyback inputs for composite blanking of the video. A

vertical blanking output pulse is provided which can drive a

G1 blanking amplifier such as the one in National’s LM2485

clamp IC. The LM1229 RGB outputs are compatible with

National’s high gain drivers (http://www.national.com).

The Deflection section uses a 12.0 MHz resonator and with

it the horizontal processor is capable of locking to seven

different television signal formats, 15.734, 28.1, 31.468,

33.7, 37.9, 45.0, and 48.08 kHz by configuring two external

tri-state pins. The resonator frequency can be scaled up or

down by as much as 5% to accommodate custom scan

frequencies, however all scan modes will be scaled up or

down by the same percentage. Additional inputs are pro-

vided for H and V synchronization, X-Ray protection, V scan

protection, and H and V EHT compensation. Deflection out-

put signals are provided for horizontal drive, variable ampli-

tude vertical ramp, vertical ramp reference voltage, variable

amplitude dynamic focus, and E-W correction with DC level

adjustment for size.

A status register is also provided for the system microcon-

troller to read and check for failure conditions.

The IC is packaged in an industry standard 64 lead LQFP

molded plastic package.

Features

n Fully bus controllable via an I

n Contrast control for simultaneously adjusting the RGB

n Gain controls for aligning the CRT color temperature.

output peak to peak levels.

C Compatible CMOS TV RGB and Deflection Processor

C compatible interface for controlling all the param-

C compatible interface.

DS201187

n Color tracking brightness control for maintaining color

n Black level clamping to ensure output level stability. The

n Digital or analog RGB OSD inputs, with adjustable

n Choice of four levels of OSD amplitude.

n Window highlight using the OSD Transparency feature.

n ABL input for reducing the video contrast when the CRT

n Horizontal and/or vertical blanking directly from

n Matched to National’s driver and clamp IC families

n Black level output adjustable from 0.5V to 1.4V for

n Three DAC outputs for setting CRT cathode bias, which

n Spot killer which blanks the video outputs when V

n RGB Power Saving Mode with 35% power reduction.

n Support for seven different TV signal formats.

n RGB blanking for scan loss protection.

n I

n Programmable duration 5V vertical blanking output

n Uses a low cost resonator.

n Status register indicating vertical scan loss, X-Ray,

n Blanks the RGB outputs whenever the loss of vertical

n Independent control over horizontal and vertical sync

Applications

n Television deflection and RGB video processing with

temperature throughout the full range of adjustment.

polarity of the logic pulse input is register selectable.

transparency available in the digital mode and clamping

in the analog mode for black level stability.

beam current exceeds the predetermined threshold set

by an external resistor.

deflection signals. The blanking can be disabled, if

desired.

(http://www.national.com).

compatibility with NSC CRT driver IC’s with or without

PNP transistor buffers.

can be set to full or half scale like the LM1267 series of

preamplifiers.

falls below the specified threshold.

pincushion, pin balance, trapezoidal, parallelogram, top

and bottom corner corrections, vertical S and C

correction, and dynamic focus amplitude.

pulse.

horizontal flyback and horizontal lock status.

scan is detected.

input polarities.

National’s CRT drivers.

C control over horizontal and vertical position and size,

www.national.com

June 2005

Related parts for LM1229YA

LM1229YA Summary of contents

Page 1

... Contrast control for simultaneously adjusting the RGB output peak to peak levels. n Gain controls for aligning the CRT color temperature. © 2005 National Semiconductor Corporation n Color tracking brightness control for maintaining color temperature throughout the full range of adjustment. n Black level clamping to ensure output level stability. The polarity of the logic pulse input is register selectable ...

Page 2

... LM1229 Package and Pinout Non-Exposed DAP — NS Package Number VEC64A www.national.com Non-Exposed DAP — Order Number LM1229VEC Exposed DAP — Order Number LM1229YA Exposed DAP — NS Package Number VXE64A FIGURE 1. 2 20118701 ...

Page 3

... Maximum contrast attenuation. V MIN A V MAX @ A Gain attenuation V 50% GAIN (Notes 1, Thermal Resistance LM1229YA (θ DAP not soldered Thermal Resistance LM1229YA (θ DAP soldered Junction Temperature (T ESD Susceptibility (Note 4) ESD Machine Model (Note 13) 6.0V Storage Temperature 1.0 mA Lead Temperature (Soldering, 10 sec.) –0.5V ≤ V ≤ ...

Page 4

Video Signal Electrical Characteristics Unless otherwise noted 25˚ (Note 7) for Min and Max parameters and (Note 6) for Typicals. Symbol Parameter A / Maximum gain attenuation. V MIN GAIN A V MAX GAIN A Maximum ...

Page 5

OSD Electrical Characteristics Unless otherwise noted 25˚ Symbol Parameter BOTH MODES I Low input current (OSD and LOW Enable). I High input current (OSD and HIGH Enable). SEP Crosstalk from video 10 kHz SEP Crosstalk from ...

Page 6

Deflection Signal Characteristics Unless otherwise noted 25˚ eters and (Note 6) for Typicals. Symbol Parameter I HDRIVE Max sink current HDO V HDRIVE Max high level output HDOH voltage δ HDRIVE Duty cycle t Delay to ...

Page 7

System Interface Signal Characteristics Unless otherwise noted 25˚ for Min and Max parameters and (Note 6) for Typicals. Symbol Parameter I Logic low input current L (SCL, SDA, HSYNC, VSYNC) I Logic high input current H ...

Page 8

Note 13: Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200 pF cap is charged to the specific voltage, then discharged directly into the IC with no external series resistor (resistance of discharge path must be under ...

Page 9

LM1229 Test Circuit (Continued) FIGURE 2. LM1229 Test Circuit 9 20118702 www.national.com ...

Page 10

Application Information PIN CONNECTIONS Pin Pin Name No ALC 2 C OSC 3 VDRIVE OUT 4 VDRIVE REF 5 V Caps REF VEHT1 9 VEHT2 www.national.com Schematic C is the feedback loop filter ...

Page 11

Application Information Pin Pin Name No OUT 11 FOCUS OUT V & GND CC 14 HDRIVE OUT 15 SCL 16 SDA (Continued) Schematic EW pincushion, trapezoid and top and bottom corners. Its lowest voltage is in the middle ...

Page 12

Application Information Pin Pin Name No. 18 Horizontal Flyback 19 FREQ1 22 FREQ2 20 HEHT 21 REHT1 24 REHT2 25 FILTER2 28 FILTER1 www.national.com (Continued) Schematic The input is a threshold detector at approximately 2.4V limit the combined ...

Page 13

Application Information Pin Pin Name No. 31 HOSC2 32 HOSC1 34 XRAY 35 HSYNC 36 VSYNC 37 DAC 3 Output 38 DAC 2 Output 39 DAC 1 Output 40 VBLANK OUT (Continued) Schematic The oscillator can be a standard 12 ...

Page 14

Application Information Pin Pin Name No. 41 Green OSD 42 Red OSD 43 Blue OSD (Digital Mode) 41 Green OSD 42 Red OSD 43 Blue OSD (Analog Mode) 44 OSD Enable 45 Green Video In 46 Red Video In 47 ...

Page 15

Application Information Pin Pin Name No. 51 ABL REF EXT 57 Blue Output 58 Red Output 59 Green Output 62 Vertical Flyback (Continued) Schematic The Automatic Beam Limiter input is biased to the desired beam current limit ...

Page 16

Application Information BLANKING The pin 18 horizontal flyback input switches at about 2.4V based on an internal reference. A large amplitude input pulse is more desireable since it reduces the rise time at pin 18. The component values shown in ...

Page 17

... OSD at the video outputs. This is still gated by the OSD Enable input level. See Tables 2, 3 for details. National Semiconductor does not recommend using the OSD inputs with both analog and digital sources in the same design. When configured for analog, the OSD inputs are vulnerable to digital logic levels and damage could occur to the LM1229 unless 100Ω ...

Page 18

Tables These are the tables which are referenced in the text. TRANS ENABLE 0 0 Normal video display Foreground and background determined by OSD inputs Normal video display Foreground and background determined by OSD ...

Page 19

... LM1229 for writing is 0xBA (10111010b) and the address for reading is 0xBB (10111011b). The develop- ment software provided by National Semiconductor will au- tomatically take care of the difference between the read and write addresses if the target address under the communica- tions tab is set to 0xBA ...

Page 20

Microcontroller Interface conductor may use some additional addresses for produc- tion testing. Writing to an address outside the ranges shown here could have unpredictable or even destructive results. Note the address gap between the RGB and deflection control registers. This ...

Page 21

Application Register Detail GREEN Gain Control Register Addr Bit 7 GREEN GAIN 0x01 X Bits 6–0: Sets the gain level of the green video channel. A value of 0x7F generates the maximum green gain. A value of 0x00 generates the ...

Page 22

Application Register Detail (0V–2.1V). Bit 4: When set to 0, vertical blanking of the RGB outputs is disabled. When set to 1, vertical blanking is enabled. Bit 3: When set to 0, the LM1229 clamps the input video when the ...

Page 23

Application Register Detail HORIZONTAL EHT CORRECTION Register Addr Bit 7 HEHT 0x42 EQPRM Bit 7: When this bit attempt is made to remove HSYNC equalizing pulses. When set HSYNC equalizing pulses are removed. ...

Page 24

Application Register Detail Bits 7–0: Sets the DC level of the vertical ramp that is used to move the picture up and down typical application, a setting of 0xFF will move the raster image to the lowest position ...

Page 25

Application Register Detail VERTICAL BLANKING OUTPUT Register Addr Bit 7 VBLANK 0x51 X Bits 6–0: These bits determine the duration of the vertical blanking output in horizontal lines, as counted by the horizontal sync input. (Continued) Bit 6 Bit 5 ...

Page 26

... Physical Dimensions www.national.com inches (millimeters) unless otherwise noted Order Number LM1229VEC NS Package Number VEC64A Order Number LM1229YA NS Package Number VXE64A 26 ...

Page 27

... BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. ...

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