LM1229YA National Semiconductor, LM1229YA Datasheet - Page 22

• Manufacturer Part Number: LM1229YA
• Description: I2C Compatible CMOS TV RGB and Deflection Processor
• Manufacturer: National Semiconductor

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Application Register Detail
Bit 4: When set to 0, vertical blanking of the RGB outputs is disabled. When set to 1, vertical blanking is enabled.
Bit 3: When set to 0, the LM1229 clamps the input video when the input clamp pulse is high. When set to 1 the LM1229 expects
Bit 2: When set to 0, horizontal blanking at the RGB outputs is disabled. When set to 1, horizontal blanking is enabled.
Bit 1: When set to 0, the LM1229 is in normal operation. When set to 1, it is put into the power save mode for reduced power
Bit 0: When set to 0, normal video appears at the RGB outputs. When set to 1, the RGB outputs are set to the blanking level as
OSD TRANSPARENCY
Bits 6–0: These bits determine the amount of video in the OSD background at the times when the OSD Enable input is active
OSD Control
Bit 7:
Bit 5:
Bit 4:
Bit 3:
Bits 1–0: These bits determine the contrast level of the OSD. Refer to Table 3 for amplitudes.
RESET
Bit 0: Setting this bit to a 1 causes a software reset. All registers (except this one) are loaded with their default values. All
STATUS
Bit 3: This is the Vertical Protection status. This bit is a 0 for normal operation, and is a 1 if Vertical Protection is triggered and
Bit 2: This bit is 0 if X-Ray is not triggered, 1 if X-Ray triggered. It will reset to 0 when V
Bit 1: Flyback pulse, 0 if good flyback pulse present, 1 if bad flyback pulse or no flyback pulse.
Bit 0: This is the horizontal deflection lock bit. It is 1 if HSYNC is present and the PLL is locked to it. It is a 0 if no HSYNC is
HORIZONTAL POSITION
Bits 7–0: Sets the horizontal position of the picture on the CRT. When set to minimum the picture is to the left, and when set to
Register
Register
OSD TRANS
Register
STATUS
Register
RESET
HPOS
OSD
Register
(0V–2.1V).
a negative going pulse.
consumption.
given in the specification section.
operations currently in progress are aborted (except for I
has been completed.
the R, G, B, video outputs are blanked. This will reset to 0 when a good vertical drive signal is present.
present or if the PLL is not locked to HSYNC.
and when there is no OSD foreground. When set to 0x00, the video background is at minimum contrast and when set
to 0x7F, the video background is at maximum contrast.
This is the OSD override bit. This will be read as a 0 for normal operation. When set to a 1, the video outputs are
disconnected and OSD only is displayed. This is useful for the OSD display of special conditions such as “No Signal”,
or other information to the user.
This bit controls whether the analog OSD gain is set to maximum. When this bit is a 0 and bit 4 is a 1, the analog OSD
output levels are determined by the input level and OSD_Cont[1:0]. When this bit is a 1 and DA is a 1, the output levels
are determined by the input level only, with a gain of 4.14. When DA is a 0 for digital OSD inputs, this bit has no effect.
See Table 3.
When set to a 0, the LM1229 is configured for digital OSD inputs. When set to a 1, the OSD inputs are configured for
0V–0.7V analog.
When set to a 0, the OSD background is determined by the OSD Enable input, such that when the enable is active the
video is set to black. When this bit is set to a 1 the OSD background is video attenuated by the OSD Transparency
register, 0x0A, but only while the OSD Enable input is a 1. See Table 2.
maximum the picture is to the right.
Addr
0x0B
Addr
0x40
Addr
0x0C
Addr
0x41
Addr
0x0A
Bit 7
OOR
Bit 7
Bit 7
Bit 7
X
X
Bit 7
X
Bit 6
Bit 6
X
Bit 6
X
Bit 6
X
Bit 6
(Continued)
Bit 5
AUX
Bit 5
X
Bit 5
Bit 5
X
Bit 5
2
22
C transactions). This bit automatically clears itself when the reset
Bit 4
Bit 4
DA
X
Bit 4
Bit 4
X
Bit 4
HPOS[7:0]
OSD TRANS[6:0]
TRANS
VPROT
Bit 3
Bit 3
Bit 3
Bit 3
X
Bit 3
CC
Bit 2
XRay
Bit 2
≤ 4V.
Bit 2
X
Bit 2
Bit 2
X
Bit 1
Bit 1
FBP
Bit 1
OSD_Cont[1:0]
Bit 1
Bit 1
X
HLOCK
Bit 0
SRST
Bit 0
Bit 0
Bit 0
Bit 0