LM1229YA National Semiconductor, LM1229YA Datasheet - Page 17

• Manufacturer Part Number: LM1229YA
• Description: I2C Compatible CMOS TV RGB and Deflection Processor
• Manufacturer: National Semiconductor

Application Information
HIGHLIGHT WINDOW
The OSD Enable input to the LM1229 can also be used to
highlight an area of the video by setting the DA bit to 0 (for
digital OSD) and the TRANS bit to a 1. The OSD TRANS
register must be set to some value higher than the
CONTRAST register. Then whenever the OSD Enable input
is high, the video will have the higher contrast setting. During
this time the RGB OSD inputs must be kept at logic 0 to
prevent them from overriding the video. Note also that since
there is only one OSD TRANS register, the highlight window
and the transparent OSD background cannot be used at the
same time.
ANALOG OSD OPERATION
The LM1229 is configured for analog OSD operation by
setting the DA bit, 0x0B[4], to 1. In this mode, the TRANS bit
and OSD TRANS register have no effect. The inputs are AC
coupled and clamped at the same time as the RGB video
inputs for OSD black level stability. These inputs are se-
lected when the OSD Enable input is high.
As in the digital mode, the contrast of the OSD can be
controlled with the OSD_Cont bits, OSD[2:1]. The AUX bit,
OSD[5], can be set to 1 to bypass the OSD contrast control
and provide full amplitude analog OSD at the video outputs.
This is still gated by the OSD Enable input level. See Tables
2, 3 for details.
National Semiconductor does not recommend using the
OSD inputs with both analog and digital sources in the same
design. When configured for analog, the OSD inputs are
vulnerable to digital logic levels and damage could occur to
the LM1229 unless 100Ω resistors are used in series with
these three inputs. These resistors should also be used in
the digital OSD mode. It very important to make the OSD
inputs AC coupled with 1000 pF capacitors in the analog
mode for black level clamping of the OSD inputs and to
prevent serious disruption of the video processing.
OSD CONTRAST
The OSD contrast amplitude is adjustable to four levels and
is set with the OSD register, OSD[1:0]. Table 3 gives the
OSD amplitudes at the RGB outputs when the RGB outputs
have each been set to 2.9V peak to peak. An “X” in the table
indicates bits which have no effect under the given condi-
tions.
DAC OUTPUTS
The three DAC outputs can be used to bias the CRT cath-
odes using one of the NSC bias IC family. The outputs are
full scale (0.5V to 4.2V) or half scale (0.5V to 2.1V). Since
the controlling registers are eight bits, the approximate step
size is either 16 mV or 8 mV. Used in combination with a
(Continued)
17
clamp IC having a gain of -30, the half scale mode gives a
bias range of 60V and a step size of 240 mV at the cathode.
HEHT COMPENSATION
The HEHT input can be used to change the horizontal phase
in response to CRT beam current loading and high voltage
droop. The compensation is register controlled and as the
input voltage drops from 3.5V to 1.5V, the resulting phase
change is a maximum of
Table 4, are for an external 20k resistor connected between
pins 21 and 24 (REHT1 and REHT2). Scaling this resistor
will change these percentages proportionately.
FREQ1 AND FREQ2
The frequency selection for these pins is shown in Table 1. A
series 100Ω resistor is recommended regardless of whether
these pins are fixed biased to V
a microcontroller. If either pin is floated for the frequency
selection, it may be desireable to use a 0.1 µF bypass
capacitor to ground in series with the 100Ω resistor to pre-
vent noise from changing the frequency selection.
ALIGNMENT
During factory alignment of the display, there are registers
which are interactive. Two of these are the vertical size,
VSIZE[7:0], and the S correction, S[6:0]. When the S correc-
tion is increased the vertical size will naturally decrease due
to the changing shape of the V
ment this can be compensated by writing both registers at
the same time. An approximate rule of thumb is to increase
the VSIZE register by the same amount as the S register.
Experimentation will give the best algorithm to use to keep
the overall vertical size constant.
The C correction adjustment is interactive with the vertical
position register VPOS[7:0]. As the C register is lowered
from the mid-range value of 0x3F (decimal 63), the position
of the raster will move up due to the changing shape of the
V
must be lowered by increasing the VPOS register value. An
approximate rule of thumb is to change the VPOS register in
the opposite direction from the C register by about half as
much. In other words, if the C register is lowered from 63 to
53, the VPOS register should be increased by about 5.
ESD PROTECTION
The LM1229 uses internal circuitry to protect itself against
damage from ESD transients. This self-protection activates
when any input pin is driven above the V
ground, and results in unpredictable behaviour during this
time. In order to avoid any unpredictable behaviour in normal
use, external protection diodes should be used on any pin
where the input can go beyond the supply voltage or below
ground. See the recommendation for the HSYNC and
VSYNC input pins.
DRIVE
output. To compensate for this the vertical position
±
4.4%. The percentages shown in
CC
DRIVE
or GND, or connected to
output. During align-
CC
supply or below
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