LM1229YA National Semiconductor, LM1229YA Datasheet - Page 20

• Manufacturer Part Number: LM1229YA
• Description: I2C Compatible CMOS TV RGB and Deflection Processor
• Manufacturer: National Semiconductor

www.national.com
DYN_FOCUS
T_CORNER
B_CORNER
SYNCPOL
BRIGHTNESS
Microcontroller Interface
conductor may use some additional addresses for produc-
tion testing. Writing to an address outside the ranges shown
here could have unpredictable or even destructive results.
Note the address gap between the RGB and deflection
control registers. This allows for future expansion of each
without changing existing registers.
GREEN GAIN
Application Register Detail
RED Gain Control
Bits 6–0 Sets the gain level of the red video channel. A value of 0x7F generates the maximum red gain. A value of 0x00
Register
PIN_BAL
OSD TRANS
VBLANK
STATUS
BLUE GAIN
CONTRAST
RED GAIN
VSIZE
HSIZE
HPOS
VPOS
HEHT
VEHT
TRAP
Register
GLOBAL
OFFSET
PAR
PIN
RESET
DAC 1
DAC 2
DAC 3
RED GAIN
C
S
OSD
Register
generates the minimum red gain.
Addr
0x4C
0x4D
0x4A
0x4B
0x4E
0x4F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x50
0x51
Addr
0x0C
0x0A
0x0B
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
Addr
0x00
Default
0xA8
0x3B
0x40
0x80
0x80
0x80
0x88
0x40
0x00
0x80
0x40
0x40
0x40
0x40
0x40
0x40
0x00
N/A
Default
0x0C
0x60
0x60
0x60
0x60
0x00
0x00
0x00
0x80
0x00
0x00
0x02
0x00
Bit 7
X
EQPRM
Bit 7
TABLE 6. Deflection Application Registers
X
X
X
X
X
X
X
X
X
X
X
INCR
OOR
Bit 7
TABLE 5. RGB Application Registers
(Continued)
X
X
X
X
X
X
X
Bit 6
XRayOff
Bit 6
Bit 6
X
X
VEHT2[7:4]
X
X
X
X
Bit 5
20
Bit 5
Bit 5
HOff
VPD
DCF
AUX
X
X
X
Register bits indicated by an “X” are not used and should be
written to with 0’s when the register is updated.
Bit 4
HPCOff
Bit 4
DA
VB
Bit 4
BRIGHTNESS[7:0]
V2D
X
X
PIN_BAL[7:0]
X
H_POS[7:0]
VSIZE[7:0]
VPOS[7:0]
PAR[7:0]
RGAIN[6:0]
DAC1[7:0]
DAC2[7:0]
DAC3[7:0]
DYN_FOCUS[6:0]
T_CORNER[6:0]
B_CORNER[6:0]
CONTRAST[6:0]
Bit 3
VBLANK[7:0]
HSIZE[6:0]
TRAP[6:0]
CLAMP
TRANS
TRANS[6:0]
GGAIN[6:0]
RGAIN[6:0]
BGAIN[6:0]
PIN[6:0]
VPROT
Bit 3
EHTEN
C[6:0]
S[6:0]
Bit 3
V1D
X
Bit 2
Bit 2
SERV
HB
XRay
DC_Offset[3:0]
Bit 2
POL
X
X
VEHT1[3:0]
Bit 1
PSAVE
Bit 1
VPOL
OSD_Cont[1:0]
Bit 1
X
FBP
HEHT[1:0]
Bit 0
BLANK
HLOCK
SRST
Bit 0
HPOL
Bit 0