LM1247 National Semiconductor, LM1247 Datasheet - Page 40

• Manufacturer Part Number: LM1247
• Description: 150 MHz I2C Compatible RGB Preamplifier with Internal 512 Character OSD ROM, 512 Character RAM and 4 DACs
• Manufacturer: National Semiconductor

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Pre-Amplifier Interface Registers
Software Reset and Test Control:
Attribute Table and Enhanced Features
Each display character and SL in the Display Page RAM will have a 4-bit Attribute Table entry associated with it. The user should
note that two-color display characters and four-color display characters use two different Attribute Tables, effectively providing 16
attributes for two-color display characters and 16 attributes for four-color display characters.
For two-color characters the attribute contains the code for the 9-bit foreground color (Color 1), the code for the 9-bit background
color (Color 0), and the character’s enhanced features (Button Box, Blinking, Heavy Box, Shadowing, Bordering, etc.).
For four-color characters the attribute contains the code for the 9-bit Color 0, the code for the 9-bit Color 1, the code for the 9-bit
Color 2, the code for the 9-bit Color 3 and the character’s enhanced features (Button Box, Blinking, Heavy Box, Shadowing,
Bordering, etc.).
TWO COLOR ATTRIBUTE FORMAT
The address range for an attribute number, 0 ≤ n ≤ 15, is provided in Table 25.
Bits 1–0
Bit 2
Bit 3
Bit 4
Bit 5
Bits 7–6
Bit 0
Bits 5–1
Bit 6
Bit 7
Bits 8–0
Bits 17–9
Bits 21–18
Bits 31–22
C2B0
Blue
X
X
Color 1 - Green
These nine bits determine the background color (color1) which is displayed when the corresponding OSD
pixel is a 0.
These nine bits determine the foreground color (color2) which is displayed when the corresponding OSD pixel
is a 1.
These are the enhanced feature (EF) bits which determine which feature is applied to the displayed character.
The features and their corresponding codes are shown in Table 24.
Reserved and should be set to zero.
C1G[2:0]
When this bit is a 1, all registers except this one are loaded with their default values. All operations are
aborted, except data transfers in progress on the I
complete.
Reserved and should be set to zero.
This bit disables the register Auto-Increment feature of the I
Auto-Increment is disabled and when a 0, AI is enabled.
Reserved and should be set to zero.
X
ATT2C1n (0x8441+n
ATT2C3n (0x8443+n
These determine the optimum frequency range of the Phase Locked Loop. Please see Table 3 for
recommended register values as a function of horizontal scan rate and the Pixels per Line register,
0x8401[7:5].
This is the Vertical Blanking register. When this bit is a 1, vertical blanking is gated to the video outputs.
When set to a 0, the video outputs do not have vertical blanking.
This is the OSD override bit. This should be set to 0 for normal operation. When set to a 1, the video
outputs are disconnected and OSD only is displayed. This is useful for the OSD display of special
conditions such as “No Signal” and “Input Signal Out of Range”, to avoid seeing unsynchronized video.
Reserved and should be set to zero.
This is the Clamp Polarity bit. When set to a 0, the LM1247 expects a positive going clamp pulse.
When set to a 1, the expected pulse is negative going.
Reserved and should be set to zero.
Res’d
X
X
Reserved
X
Color 1 - Red
AID
C1R[2:0]
*
*
4)
4)
X
X
X
SRTSTCTRL (0x843F)
(Continued)
X
X
Color 0 - Blue
40
C0B[2:0]
Reserved
X
X
2
C compatible bus. This bit clears itself when the reset is
X
X
2
C compatible protocol. When set to a 1
ATT2C0n (0x8440+n
ATT2C2n (0x8442+n
Color 0 - Green
Enhanced Feature
C0G[2:0]
X
EFB[3:0]
Reset
SRST
*
*
4)
4)
Color 0 - Red
C0R[2:0]
Color 1 -
C1B[2:1]