LM1247 National Semiconductor, LM1247 Datasheet - Page 5

• Manufacturer Part Number: LM1247
• Description: 150 MHz I2C Compatible RGB Preamplifier with Internal 512 Character OSD ROM, 512 Character RAM and 4 DACs
• Manufacturer: National Semiconductor

System Interface Signal Characteristics
Note 1: Limits of Absolute Maximum Ratings indicate below which damage to the device must not occur.
Note 2: Operating ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits.
Note 3: All voltages are measured with respect to GND, unless otherwise specified.
Note 4: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 5: Input from signal generator: t
Note 6: Typical specifications are specified at +25˚C and represent the most likely parametric norm.
Note 7: Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. The guaranteed specifications apply only for the test conditions
listed. Some performance characteristics may change when the device is not operated under the listed test conditions.
Note 8: The supply current specified is the quiescent current for V
therefore all the supply current is used by the pre-amp.
Note 9: Linearity Error is the maximum variation in step height of a 16 step staircase input signal waveform with a 0.7 V
with each at least 100 ns in duration.
Note 10: dt/dV
Note 11: ∆A
gain change between any two amplifiers with the contrast set to A
amplifiers’ gains might be 12.1 dB, 11.9 dB, and 11.8 dB and change to 2.2 dB, 1.9 dB and 1.7 dB respectively for contrast set to A
gain change of 10.0 dB with a tracking change of
Note 12: The ABL input provides smooth decrease in gain over the operational range of 0 dB to −5 dB: ∆A
V
Note 13: Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200 pF cap is charged to the specific voltage, then discharged directly into the
IC with no external series resistor (resistance of discharge path must be under 50Ω).
Note 14: Measure output levels of the other two undriven amplifiers relative to the driven amplifier to determine channel separation. Terminate the undriven amplifier
inputs to simulate generator loading. Repeat test at f
Note 15: A minimum pulse width of 200 ns is the guaranteed minimum for a horizontal line of 15 kHz. This limit is guaranteed by design. If a lower line rate is used
then a longer clamp pulse may be required.
Note 16: Adjust input frequency from 10 MHz (A
Note 17: Once the spot killer has been activated, the LM1247 remains in the off state until V
Hexadecimal and Binary Notation
Hexadecimal numbers appear frequently throughout this
document, representing slave and register addresses, and
register values. These appear in the format “0x...”. For ex-
ample, the slave address for writing the registers of the
LM1247 is hexadecimal BA, written as 0xBA. On the other
hand, binary values, where the individual bit values are
shown, are indicated by a trailing “b”. For example, 0xBA is
equal to 10111010b. A subset of bits within a register is
referred to by the bit numbers in brackets following the
ABL MIN GAIN
DC Offset
Contrast
Control
B, R, G
Gain
V
). Beyond −5 dB the gain characteristics, linearity and pulse response may depart from normal values.
track is a measure of the ability of any two amplifiers to track each other and quantifies the matching of the three gain stages. It is the difference in
CC
No. of Bits
= 200
7
7
3
*
(t
5.5V
–t
4.5V
)/ ((t
(Max)
(Max)
r
0x7F
0x7F
0x00
(Min)
, t
1
f
5.5V
<
1 ns.
+ t
4.5V
V
±
max reference level) to the −3 dB corner frequency (f
)) %/V, where: t
0.2 dB.
IN
(Max)
0x00
0x7F
0x05
Min
= 10 MHz for V
2
TABLE 1. Test Settings
CC
5.5V
V
C−50% and measured relative to the A
(Max)
(Max)
(Max)
and 5V Dig with R
0x7F
0x7F
0x07
SEP
is the rise or fall time at V
3
10 MHz.
5
Set V
2 V
(Max)
register value. For example, the OSD contrast bits are the
fourth and fifth bits of register 0x8438. Since the first bit is bit
0, the OSD contrast register is 0x8438[4:3].
Register Test Settings
Table 1 shows the definitions of the Test Settings 1–8 re-
ferred to in the specifications sections. Each test setting is a
combination of five hexadecimal register values, Contrast,
Gain (Blue, Red, Green) and DC offset.
0x7F
0x05
(Continued)
L
4
Test Settings
P-P
=
O
∞
to
CC
. Load resistors are not required and are not used in the test circuit,
is cycled (reduced below 0.5V and then restored to 5V).
CC
(50.4%)
= 5.5V, and t
(Max)
0x40
0x7F
0x05
−3 dB
5
V
).
max condition. For example, at A
ABL
4.5V
(50.4%)
= A(V
(Max)
0x7F
0x40
0x05
is the rise or fall time at V
P-P
6
ABL
level at the input. All 16 steps equal,
= V
V
ABL MAX GAIN
C−50%. This yields a typical
(Max)
0x7F
0x00
(Min)
0x05
7
CC
V
) – A (V
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max the three
= 4.5V.
(Max)
(Max)
0x7F
0x7F
0x05
8
ABL
=