LM1247 National Semiconductor, LM1247 Datasheet - Page 8

• Manufacturer Part Number: LM1247
• Description: 150 MHz I2C Compatible RGB Preamplifier with Internal 512 Character OSD ROM, 512 Character RAM and 4 DACs
• Manufacturer: National Semiconductor

Typical Performance Characteristics
V
= 5V, T
= 25˚C unless otherwise specified (Continued)
CC
A
20048408
FIGURE 8. ABL Gain Reduction Curve
SYSTEM INTERFACE SIGNALS
The Horizontal and Vertical Blanking and the Clamping input signals are important for proper functionality of the LM1247. Both
blanking inputs must be present for OSD synchronization. In addition, the Horizontal blanking input also assists in setting the
proper cathode black level, along with the Clamping pulse. The Vertical blanking input initiates a blanking level at the LM1247
outputs which is programmable from 3 to 127 lines (we recommend at least 10). Both horizontal and vertical blanking can be
individually disabled, if desired.
Figure 2 and Figure 3 show the case where the Horizontal and Vertical inputs are logic levels. Figure 2 shows the smaller pin 24
voltage superimposed on the horizontal blanking pulse input to the neck board with R
= 4.7k and C
= 0.1 µF. Note where the
H
17
voltage at pin 24 is clamped to about 1 volt when the pin is sinking current. Figure 3 shows the smaller pin 1 voltage
superimposed on the vertical blanking input to the neck board with C
jumpered and R
= 4.7k. These component values
4
V
correspond to the application circuit of Figure 9.
Figure 4 and Figure 5 show the case where the horizontal and vertical inputs are from deflection. Figure 4 shows the pin 24
voltage which is derived from a horizontal flyback pulse of 35V peak to peak with R
= 8.2K and C
jumpered. Figure 5 shows
H
17
the pin 1 voltage which is derived from a vertical flyback pulse of 55V peak to peak with C
= 1500 pF and R
= 120k.
4
V
Figure 6 shows the pin 23 clamp input voltage superimposed on the neck board clamp logic input pulse. R
= 1k and should be
31
chosen to limit the pin 23 voltage to about 2.5V peak to peak. This corresponds to the application circuit given in Figure 9.
CATHODE RESPONSE
Figure 7 shows the response at the red cathode for the application circuit in Figures 9, 10. The input video risetime is 1.5 ns. The
resulting leading edge has a 7.1 ns risetime and a 7.6% overshoot, while the trailing edge has a 7.1 ns risetime and a 6.9%
overshoot with an LM2467 driver.
ABL GAIN REDUCTION
The ABL function reduces the contrast level of the LM1247 as the voltage on pin 22 is lowered from V
to around 2V. Figure 8
CC
shows the amount of gain reduction as the voltage is lowered from V
(5.0V) to 2V. The gain reduction is small until V
reaches
CC
22
the knee anound 3.7V, where the slope increases. Many system designs will require about 3 dB to 5 dB of gain reduction in full
beam limiting. Additional attenuation is possible, and can be used in special circumstances. However, in this case, video
performance such as video linearity and tracking between channels will tend to depart from normal specifications.
OSD PHASE LOCKED LOOP
Table 3 shows the recommended horizontal scan rate ranges (in kHz) for each combination of PLL register setting, 0x843E [1:0],
o
and the pixels per line register setting, 0x8401 [7:5]. These ranges are recommended for chip ambient temperatures of 25
C to
o
70
C. While the OSD PLL will lock for other register combinations and at scan rates outside these ranges, the performance of the
loop will be improved if these recommendations are followed. NR means the combination of PLL and PPL is not recommended
for any scan rate.
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