UPD78320GJ-5BJ NEC, UPD78320GJ-5BJ Datasheet - Page 49

• Manufacturer Part Number: UPD78320GJ-5BJ
• Description: 16/8-BIT SINGLE-CHIP MICROCONTROLLER
• Manufacturer: NEC

7. OPERATION AFTER RESET
(reset status). If RESET input becomes high level, the reset state is released and program execution is started. Initialize
the contents of various registers in the program as required.
in particular.
Cautions 1. While RESET is active (low level), all pins remain high impedance (except WDTO, AV
acknowledge as shown in Figure 7-2.
If the RESET input pin is set to the low level, the system reset is applied and each hardware becomes as initialized status
Change the number of cycles for the programmable wait control register and the fetch cycle control register as required
The RESET input pin is equipped with an analog delay noise eliminator to prevent malfunctioning due to noise.
For reset operation upon power-up, secure the oscillation stabilization time of about 40 msec from power-up to reset
2. If RAM has been expanded externally, mount a pull-up resistor to the P90/RD and P91/WR pins. It is
RESET Input
V
possible that the P90/RD and P91/WR pins become high impedance resulting in an external RAM
contents corruption. In addition, signals may collide on the address/data bus, resulting in the
destruction of the input/output circuit.
RESET
DD
V
DD
, V
SS
, X1 and X2).
Analog
Delay
Eliminated
as Noise
Figure 7-1. Reset Signal Acknowledge
Figure 7-2. Reset Upon Power-Up
Analog
Delay
Acknowl-
edged
Reset
Oscillation
Stabilization
Time
Analog
Delay
Reset
Release
Analog
Delay
Reset
Release
PD78320, 78322
REF
, AV
DD
, AV
SS
49
,