AN1769 Freescale Semiconductor / Motorola, AN1769 Datasheet - Page 10

• Manufacturer Part Number: AN1769
• Description: Designing a Minimal PowerPC System
• Manufacturer: Freescale Semiconductor / Motorola

3.4 Collected Controls
The previous sections have provided a general overview of the memory controller; this section provides the
details. Table 1 shows most of the signals that are directly connected to the memory or I/O or are wired to
some particular state. The controls needed for burst SRAM and ßash ROM share common byte-write
enables; the memory controller signals are listed in Table 3.
10
TS
TT(0Ð4), TSIZ(0Ð2), TBST
A(0Ð1)
A(29Ð31)
AACK
TA
TEA
BWE(0Ð7)
SCS
SOE
ADSC
BAA
FCS
FOE
XCS(0Ð1)
XOE
Signal
BWE0
XCS0
XCS1
XOE
Freescale Semiconductor, Inc.
Table 3. Memory Controller Signal Handling
For More Information On This Product,
RD
WE
CS
OE
R/W
CS
Examined for start of a cycle
Examined for type of cycle
Examined for cycle destination (RAM, ROM, I/O)
Examined for byte lane enables and burst transfer
Asserted on Þnal memory transfer
Asserted per-beat on each memory transfer
Asserted on each unsupported memory transfer
Asserted on writes on individual byte lane(s)
Asserted on all SRAM accesses
Asserted on all SRAM read accesses
Asserted on all burst SRAM accesses before the Þrst cycle
Asserted on all burst SRAM accesses during cycles 2-4
Asserted on all Flash accesses
Asserted on all Flash read accesses
Asserted on all I/O accesses
Asserted on all I/O read accesses
Minimal PowerPC System Design
Figure 7. Buffered I/O Connections
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5V
I/O Device
3.3V
I/O Device
Treatment
LVT245
OE
DIR
D(0Ð7)
All
All
All
All
All
All
All
SRAM, ROM
SRAM
SRAM
SRAM
SRAM
ROM
ROM
I/O
I/O
Applies To
MOTOROLA