AN1769 Freescale Semiconductor / Motorola, AN1769 Datasheet - Page 39
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AN1769
Manufacturer Part Number
AN1769
Description
Designing a Minimal PowerPC System
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
1.AN1769.pdf
(44 pages)
MOTOROLA
Part 8 COP
The common on-chip processor (COP) function of PowerPC processors allows a remote computer system
(typically a PC with dedicated hardware and debugging software) to access and control the internal
operations of the processor. While adding a COP connection to any PowerPC system adds little to no cost,
it does add many beneÞtsÑbreakpoints, watchpoints, register and memory examination/modiÞcation and
other standard debugger features are possible through this interface.
The COP interface has a standard header for connection to the target system, based on the 0.025" square-
post 0.100" centered header assembly (often called a ÒBergÓ header). The connector typically has pin 14
removed as a connector key, as shown in Figure 28.
NOTE: There is no standardized way to number these headers; consequently, many different pin numbers
have been observed on a variety of schematics. Some are numbered top-to-bottom then left-to-right, while
others use left-to-right then top-to-bottom, while still others number the pins clockwise from pin one (as
with an IC). Regardless of any local standardization, when adding a COP port to a system, insure that the
signal placement follows that of Figure 28 when viewed from above the connector.
The COP interface connects primarily through the JTAG port of the processor, with some additional status
monitoring signals. Table 6 shows the pin deÞnitions.
1
2
3
4
5
6
Pins
TDO
QACK
TDI
TRST
RUN/STOP
VDD_SENSE
Signal
15
16
TDO
QACK
TDI
TRST
RUN
VDD
Connection
No pin
13
KEY
Freescale Semiconductor, Inc.
11
For More Information On This Product,
12
Figure 28. COP Connector Diagram
10
9
Minimal PowerPC System Design
Table 6. COP Pin Definitions
All
603e, 603ev, 740, 750
All
All
604, 604e
All
7
8
Go to: www.freescale.com
Applicable Processor
6
5
3
4
1
2
Pins 10, 12 and 14 are no-connects.
Pin 14 is not physically present
TOP VIEW
See section 8.2.
Add 2K pulldown to ground. Must be
merged with on-board TRST, if any.
Leave no-connect for all other processors.
Add 2K pullup to VDD.
Special
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