AN1769 Freescale Semiconductor / Motorola, AN1769 Datasheet - Page 12

• Manufacturer Part Number: AN1769
• Description: Designing a Minimal PowerPC System
• Manufacturer: Freescale Semiconductor / Motorola

All remaining TT codes are either address-only cycles (which are not needed), are caused by instructions
not needed in single-processor environments (for example, the eciwx, ecowx, dcbz, lwarx, and stcwx
instructions), or are reserved values. These simpliÞcations are possible because there is no need to snoop
the processor bus to maintain cache coherency.
While software should not generate such cycles, it is not reliable for a memory controller to simply ignore
them. The memory controller, as the sole target of bus transactions, must terminate unacceptable bus cycles
with TEA; otherwise, the processor will wait forever for the (ignored) cycle to complete.
When any transfer begins, the Òstart()Ó module must either assert the Òclaim_lÓ or Òdoerr_lÓ signal to cause
the appropriate actions to conclude the transfer cycle (which is handled in the bus state machine Òcycler()Ó).
The general architecture of Òstart()Ó is shown in Figure 9.
The TT(0Ð4) signals do not change during the address tenure, whether burst or single-beat, so the outputs
remain valid until the memory controller asserts AACK. The Òstart()Ó module provides the global
CLAIM_L signal, used by other modules to detect whether a cycle is in-progress, or the DOERR_L signal,
used to terminate unclaimed cycles, and a write signal (WE_L) to determine that the cycle is a write cycle.
These signals are used exclusively by other modules, and remain valid until the memory controller
completes the cycle by asserting AACK.
The VHDL code for this module is:
12
0
0
0
0
TT0
------------------------------------------------------------------------------------------------
-- TTDEC.VHD
--
-- TTDEC() monitors the TT bus and determines whether the TT is of interest to
-- the MC or not. If so, a signal is provided for start, and tt_we_L reflects
-- the read/write status.
--
-- NOTE: TTDEC must not be optimized or errors will occur when hierarchical
--
--
--
0
0
1
1
TT1
optimization is performed (TT1 and TT2 will be optimized away, making it
impossible to connect TTDEC to MC-- this is a bug in ViewSynthesis).
Recommended procedure is to dissolve TTDEC into it's parent level MC
0
1
0
1
TT2
TT(0Ð4)
1
1
1
1
TT3
AACK
CLK
RST
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TS
For More Information On This Product,
0
0
0
0
TT4
Minimal PowerPC System Design
Figure 9. Start Detector Module
5
Write-with-ßush
Write-with-kill
Read
Read-with-intent-to-modify
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Table 4. TT Encoding
Transaction
ttdec()
start()
Single-beat or burst write
Burst write
Single-beat or burst read
Burst read
WE_L
CLAIM_L
DOERR_L
Memory Controller Action
MOTOROLA