AN1769 Freescale Semiconductor / Motorola, AN1769 Datasheet - Page 14

• Manufacturer Part Number: AN1769
• Description: Designing a Minimal PowerPC System
• Manufacturer: Freescale Semiconductor / Motorola

3.5.2 Byte Write Enable
The next group of signals to generate are the byte lane write enables BWE(0Ð7). These signals are generated
by using the transfer size signals TSIZ(0Ð2) along with the lower address bus signals A(29Ð31) to determine
which byte lanes should be active.
14
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--==============================================================================================
-- START
------------------------------------------------------------------------------------------------
ENTITY START is
end; --PORT DEFINITION AND ENTITY
------------------------------------------------------------------------------------------------
ARCHITECTURE BEHAVIOR OF START is
BEGIN
END BEHAVIOR;
------------------------------------------------------------------------------------------------
-- Derive a D flop to maintain selected status. The register must be globally clocked to fit
-- well in the Lattice 2xxx FPGA architecture, where clocks and resets are global (or expensive).
monitor : PROCESS( clk, rst_L )
BEGIN
END PROCESS;
PORT( tt_take
IF (rst_L = '0') THEN
ELSIF (clk'EVENT and clk = '1') THEN
END IF;
);
we_L
claim_L <= '1';
doerr_L <= '1';
IF (
ELSE
END IF;
IF ( (ts_L = '0'
ELSE
END IF;
tt_we_L
ts_L
aack_L
clk
rst_L
claim_L
doerr_L
we_L
doerr_L <= '1';
or (doerr_L = '0' and aack_L = '1')) THEN
doerr_L <= '0';
or (claim_L = '0' and aack_L = '1')) THEN
claim_L <= '0';
we_L
claim_L <= '1';
we_L
(ts_L = '0'
<= '1';
Freescale Semiconductor, Inc.
<= tt_we_L;
<= '1';
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Minimal PowerPC System Design
: in
: in
: in
: in
: in
: in
: buffer std_logic;
: buffer std_logic;
: buffer std_logic
and tt_take = '0')
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and tt_take = '1')
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
-- asserted if good TT selection.
-- asserted if good TT is write.
-- transfer start strobe.
-- asserted on transfer complete.
-- bus clock.
-- system reset.
-- asserted when cycle is claimed.
-- asserted when cycle not claimed.
-- byte lane write selects.
-- TS and something we want.
-- claimed, but not AACK'd
-- else AACK or no-claim
-- TS and something we dont' want.
-- errored, but not AACK'd
-- else AACK or claim
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