AN2329 Freescale Semiconductor / Motorola, AN2329 Datasheet

AN2329

Manufacturer Part Number

AN2329

Description

Interfacing the MSC8101 to SDRAM on the MSC8101ADS

Manufacturer

Freescale Semiconductor / Motorola

Datasheet

1.AN2329.pdf (28 pages)

Current page: 1 of 28
Download datasheet (671Kb)

Application Note

AN2329/D

Rev. 0, 9/2002

Interfacing the

MSC8101 to SDRAM

on the MSC8101ADS

by Marwan Younis

Al-saiegh

CONTENTS

1 SDRAM Machine Basics 1

2 MT48LC2M32B2TG

2.1 SDRAM Main Interface

2.2 SDRAM Operations..... 6

2.3 SDRAM Row and

2.4 SDRAM Timing

3 Programming the

3.1 Selecting the SDRAM

3.2 Page Hit Checking .... 11

3.3 Partitioning the

3.4 Memory Controller

3.5 SDRAM Machine

4 Related Reading .......... 25

SDRAM Device.............. 4

MSC8101 SDRAM

Machine ....................... 11

Commands................... 5

Column Addressing ..... 6

Diagrams..................... 7

Machine..................... 11

System Bus................. 11

Bank Registers........... 15

Initialization on the

MSC8101ADS ........... 23

Synchronous DRAM (SDRAM) is one of the most cost effective read/write memories on the market,

offering high-performance throughput with the cost benefits of a commodity item. In synchronous

DRAM, all the memory signal timing relates to a single clock that allows SDRAM to provide

significantly faster access time than DRAM.

This application note discusses the interface between the Motorola MSC8101 memory controller

(SDRAM machine) and an example JEDEC-compatible MICRON SDRAM device, which is referred to

as the MT48LC2M32B2TG device. It begins with an overview of SDRAM basics, including the signals

for interfacing an SDRAM device to the MSC8101 device, and then discusses the MSC8101 (DSP side)

SDRAM machine. Finally, the application note shows how to initialize SDRAM using the MSC8101

SDRAM machine.

Figure 1 shows the MSC8101 memory controller (MEMC), which consists of three user-programmable

machines (UPMs), one general-purpose chip-select machine (GPCM), and one SDRAM machine. The

SDRAM machine is available only on the system bus, which can assign memory banks to the SDRAM

machine. Features of the SDRAM machine include:

• Control functions and signals for a glueless connection to JEDEC-compliant SDRAM devices

• Two types of page mode, each selectable per memory bank: back-to-back page mode for consecutive

• 2-, 4-, and 8-way bank interleaving

• An SDRAM port size of 64 bits, 32 bits, 16 bits, or 8 bits

• External address and/or command line buffering

The SDRAM machine operates in one of two bus modes, Single-Master Bus mode and Multi-Master Bus

mode. In Single-Master Bus mode, the MSC8101 device is the only master on the system bus, and the

MSC8101 device interfaces directly to memory and slave peripherals. It sends address and control signals

for a direct, glueless interface to the SDRAM. There is no need for external address latching because the

MSC8101 MEMC handles address multiplexing.

and back-to-back accesses and page mode for intermittent accesses

SDRAM Machine Basics

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

Related parts for AN2329

AN2329 Summary of contents

Page 1

... Freescale Semiconductor, Inc. Application Note AN2329/D Rev. 0, 9/2002 Interfacing the MSC8101 to SDRAM on the MSC8101ADS by Marwan Younis Synchronous DRAM (SDRAM) is one of the most cost effective read/write memories on the market, Al-saiegh offering high-performance throughput with the cost benefits of a commodity item. In synchronous DRAM, all the memory signal timing relates to a single clock that allows SDRAM to provide CONTENTS significantly faster access time than DRAM ...

Page 2

SDRAM Machine Basics System Bus Address[0–31] System Bus Data[0–63] System Bus Slave System Bus-to-Local Bus Transactions Local Slave CPM/Local Master Local Address [0–31] Local Data [0–63] Figure 2 depicts Single-Master Bus mode. In system bus Multi-Master Bus mode, there are ...

Page 3

Freescale Semiconductor, Inc. MSC8101 PSDDQM[0–7] A[17] PSDA10 12-bit A[19–28] D[0–63] CS[0–7] PSDRAS PSDWE PSDCAS CLKOUT CS2 Figure 2. Single-Bus Mode SDRAM Hardware Interconnect to MSC8101 SDRAM Machine Table 1 lists the key components of the SDRAM architecture of the SDRAM ...

Page 4

MT48LC2M32B2TG SDRAM Device Component Pipelined Operation A10/Auto Precharge Refresh and Refresh Counter CAS Latency 2 MT48LC2M32B2TG SDRAM Device The MT48LC2M32B2TG Figure 3). This register configures basic SDRAM device operation, such as the following: • latency ( CAS ...

Page 5

Freescale Semiconductor, Inc. When WB (shown in Figure 3) is cleared, the burst length programmed via BL applies to both read and write bursts. When WB is set to 1, the programmed burst length applies to read bursts, but write ...

Page 6

MT48LC2M32B2TG SDRAM Device 2.2 SDRAM Operations Table 2 shows the functions of the SDRAM device and the pins associated with them. Command Command Inhibit (NOP) No Operation (NOP) Active (Select bank and activate Row) READ (Select bank and column, and ...

Page 7

Freescale Semiconductor, Inc. no full address visibility. When BCR[EAV] is set, bank select signals are not driven on the address bus. Bank select lines are used to drive the the BA[0–1] environments. The row address lines are used to activate ...

Page 8

MT48LC2M32B2TG SDRAM Device Name tAC2 tLZ t32a t12a t11 tOH tHZ2 t10 tAS tAH CLKOUT CS BA0, BA1 RAS CAS WE SDA10 ADDRESS Data PSDVAL TA 8 Freescale Semiconductor, Inc. Table 3. Single Read Transaction Min Max 8 Access time ...

Page 9

Freescale Semiconductor, Inc. Name t34 t32a t31 t33a tDS tDH tAS tAH RAS-to-CAS CLKOUT t34 CS t34 t34 BANK BA0,BA1 t34 t34 RAS t34 CAS WE t32a t32a SDA10 tAS t32a t32a Row ADDRESS Data PSDVAL TA Name tAC2 tLZ ...

Page 10

MT48LC2M32B2TG SDRAM Device Name t32a t12a t10 t11 tHZ2 tAS tAH CLKOUT CS BA0. BA1 RAS CAS WE SDA10 ADDRESS Data PSDVAL TA DQM[0–7] Name t34 t32a t34 t33a 10 Freescale Semiconductor, Inc. Table 5. Read Burst from SDRAM (Continued) ...

Page 11

Freescale Semiconductor, Inc. Name t31 tDS tDH 3 Programming the MSC8101 SDRAM Machine This section discusses how to interface the MICRON MT48LC2M32B2 SDRAM to the MSC8101 SDRAM machine. To program the SDRAM machine to communicate with the SDRAM correctly, complete ...

Page 12

Programming the MSC8101 SDRAM Machine A[0–7] MSB of start address A[0–8] MSB of start address When the system bus address bus is partitioned for page-based interleaving, the LSB vary between a 32-bit and a 64-bit port size because address lines ...

Page 13

Freescale Semiconductor, Inc. Table 12. SDRAM Device Address Port During Driven Signals System bus Bus partition The / READ WRITE address lines to activate the bank, the MSC8101 must either read or write to that specific bank. At this point, ...

Page 14

Programming the MSC8101 SDRAM Machine A0 — — A10 A11 A12 Figure 9. MSC8101 SDRAM Address Multiplexing. Note: Partitioning is affected if a different SDRAM is used. Usually the number of row and column address lines varies ...

Page 15

Freescale Semiconductor, Inc. Table 18. SDRAM Device Address Port During READ/WRITE for 64-Bit Port Size Driven Signals System bus partition Table 19. SDRAM Device Address Port During READ/WRITE for 32-Bit Port Size Driven Signals System bus partition 3.4 Memory Controller ...

Page 16

Programming the MSC8101 SDRAM Machine Name Reset BA 1 Base Address 0–16 The upper 17 bits of each base address register are compared to the address on the address bus to determine if the bus master is accessing a memory ...

Page 17

Freescale Semiconductor, Inc. Name Reset Valid Bit 31 Indicates that the contents of the BRx and ORx pair are valid. The CS signal does not assert until V is set. An access to a region with no ...

Page 18

Programming the MSC8101 SDRAM Machine Name Reset BPD 0 Banks Per Device 17–18 Sets the number of internal banks per SDRAM device. Note that for 128-MB SDRAMs, BPD must have a value 01. 0 ROWST Row Start ...

Page 19

Freescale Semiconductor, Inc. PSDMR Bit PBI RFEN TYPE RESET RFRC PRETOACT TYPE RESET PSDMR configures operations pertaining to the SDRAM machine on the system bus. All possible bit ...

Page 20

Programming the MSC8101 SDRAM Machine Name Reset 0 SDAM 5–7 BSMA 0 8–10 0 SDA10 11–13 20 Freescale Semiconductor, Inc. Table 22. PSDMR Settings (Continued) Description Address Multiplex Size Determines how the address of the current memory cycle can be ...

Page 21

Freescale Semiconductor, Inc. Table 22. PSDMR Settings (Continued) Name Reset Description RFRC 0 Refresh Recovery 14–16 Defines the earliest timing for an activate command after a the refresh recovery interval in clock cycles. PRETOACT 0 Precharge to Activate Interval 17–19 ...

Page 22

Programming the MSC8101 SDRAM Machine Name Reset 0 BUFCMD 30–31 PSRT 60x Bus-Assigned SDRAM Refresh Timer Bit 0 TYPE RESET 0 PSRT determines the timer period for SDRAM refresh requests. Name Reset PSRT 0 Refresh Timer Period ...

Page 23

Freescale Semiconductor, Inc. MPTPR Memory Refresh Timer Prescaler Register Bit 0 1 TYPE RESET 0 0 MPTPR determines the period of the memory refresh timer input clock. It divides the bus clock Name Reset PTP 0 Memory Timers Prescaler 0–5 ...

Page 24

Programming the MSC8101 SDRAM Machine writemmr32 PSDMR 0xc2689212 writemem32 0x20000020 0x0 writemmr32 PSDMR 0xaa689212 writemem32 0x20000020 0x0 writemmr32 PSDMR 0x8a689212 writemem32 0x20000000 0x0 writemem32 0x20000000 0x0 writemem32 0x20000000 0x0 writemem32 0x20000000 0x0 writemem32 0x20000000 0x0 writemem32 0x20000000 0x0 writemem32 0x20000000 ...

Page 25

Freescale Semiconductor, Inc. writemmr32 BR2 0x20001841 writemmr32 PSDMR 0xc2849312 writemem32 0x20000020 0x0 writemmr32 PSDMR 0xaa849312 writemem32 0x20000020 0x0 writemmr32 PSDMR 0x8a849312 writemem32 0x20000000 0x0 writemem32 0x20000000 0x0 writemem32 0x20000000 0x0 writemem32 0x20000000 0x0 writemem32 0x20000000 0x0 writemem32 0x20000000 0x0 writemem32 ...

Page 26

Related Reading NOTES: 26 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...

Page 27

Freescale Semiconductor, Inc. NOTES: For More Information On This Product, Go to: www.freescale.com Related Reading 27 ...

Page 28

... StarCore are trademarks of Motorola, Inc. Metrowerks and CodeWarrior are registered trademarks of Metrowerks Corp. in the U.S. and/or other countries. All other product or service names are the property of their respective owners. Motorola, Inc Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2002 AN2329/D For More Information On This Product, Go to: www.freescale.com ...

Related keywords

AN2329 datasheet
AN2329 data sheet
AN2329 pdf datasheet
AN2329 component
AN2329 part
AN2329 distributor
AN2329 RoHS
AN2329 datasheet download