FDC37M60X SMSC Corporation, FDC37M60X Datasheet - Page 117

• Manufacturer Part Number: FDC37M60X
• Description: ENHANCED SUPER I/O CONTROLLER WITH INFRARED SUPPORT
• Manufacturer: SMSC Corporation

Status Register
This register is cleared on a reset. This register
is read-only for the Host and read/write by the
FDC37M60x CPU.
UD Writable by FDC37M60x CPU. These bits
are user-definable.
C/D (Command Data) - This bit specifies
whether the input data register contains data or
a command (0 = data, 1 = command). During a
host data/command write operation, this bit is
set to "1" if SA2 = 1 or reset to "0" if SA2 = 0.
IBF (Input Buffer Full) - This flag is set to “1”
whenever the host system writes data into the
input data register. Setting this flag activates
the FDC37M60x CPU's nIBF (MIRQ) interrupt if
enabled. When the FDC37M60x CPU reads the
input
automatically
UD
D7
data
register
reset
KCLK
KDAT
MCLK
MDAT
Host I/F Data Reg
Host I/F Status Reg
UD
D6
and
(DBB),
DESCRIPTION
the
UD
D5
this
interrupt
N/A: Not Applicable
bit
Table 51 - Resets
Table 50 - Status Register
UD
D4
is
is
117
HARDWARE RESET (RESET)
cleared. There is no output pin associated with
this internal signal.
OBF
whenever the FDC37M60x CPU write to the
output data register (DBB).
system reads the output data register, this bit is
automatically reset.
EXTERNAL CLOCK SIGNAL
The FDC37M60x Keyboard Controller clock
source is a 12 MHz clock generated from a
14.318 MHz clock. The reset pulse must last for
at least 24 16 MHz clock periods. The pulse-
width requirement applies to both internally (Vcc
POR) and externally generated reset signals. In
powerdown mode, the external clock signal is
not loaded by the chip.
DEFAULT RESET CONDITIONS
The FDC37M60x has one source of reset: an
external reset via the RESET_DRV pin. Refer to
Table 51 for the effect of each type of reset on
the internal registers.
C/D
D3
(Output Buffer Full) - This flag is set to
Weak High
Weak High
Weak High
Weak High
00H
N/A
UD
D2
IBF
D1
When the host
OBF
D0