FDC37M60X SMSC Corporation, FDC37M60X Datasheet - Page 127

• Manufacturer Part Number: FDC37M60X
• Description: ENHANCED SUPER I/O CONTROLLER WITH INFRARED SUPPORT
• Manufacturer: SMSC Corporation

Chip Level (Global) Control/Configuration
Registers[0x00-0x2F]
The chip-level (global) registers lie in the
address range [0x00-0x2F]. The design MUST
use all 8 bits of the ADDRESS Port for register
selection. All unimplemented registers and bits
ignore writes and return zero when read.
Config Control
Default = 0x00
on Vcc POR or
Reset_Drv
Logical Device #
Default = 0x00
on Vcc POR or
Reset_Drv
Card Level
Reserved
Device ID
Hard wired
= 0x47
Device Rev
Hard wired
= Current Revision
REGISTER
0x08 - 0x1F Reserved - Writes are ignored, reads return 0.
0x03 - 0x06 Reserved - Writes are ignored, reads return 0.
ADDRESS
0x07 R/W
0x02 W
0x20 R
0x21 R
0x00 -
0x01
Chip (Global) Control Registers
Table 53 - Chip Level Registers
Chip Level, SMSC Defined
Reserved - Writes are ignored, reads return 0.
The hardware automatically clears this bit after the
write, there is no need for software to clear the bits.
Bit 0 = 1: Soft Reset. Refer to the "Configuration
Registers" table for the soft reset value for each
register.
A write to this register selects the current logical
device.
configuration registers for each logical device.
Note: the Activate command operates only on the
selected logical device.
A read only register which provides device
identification. Bits[7:0] = 0x47 when read.
A read only register which provides device revision
information. Bits[7:0] = 0x00 when read.
This allows access to the control and
127
The INDEX PORT is used to select a
configuration register in the chip.
PORT
register. These registers are accessable only in
the Configuration Mode.
DESCRIPTION
is then used to access the selected
The DATA
STATE
C
C
C
C