IDT72V825L15PF IDT, Integrated Device Technology Inc, IDT72V825L15PF Datasheet
IDT72V825L15PF
Specifications of IDT72V825L15PF
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IDT72V825L15PF Summary of contents
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FEATURES: • • • • • The IDT72V805 is equivalent to two IDT72V205 256 x 18 FIFOs • • • • • The IDT72V815 is equivalent to two IDT72V215 512 x 18 FIFOs • • • • • The IDT72V825 ...
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IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18 DESCRIPTION (CONTINUED) First-Out (FIFO) memories with clocked read and write controls. These FIFOs are applicable for a wide variety of data buffering ...
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IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18 PIN DESCRIPTION Symbol Name I/O DA –DA Data Inputs - RSA Reset RSB WCLKA Write Clock WCLKB ...
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IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18 ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage STG Temperature I DC Output Current OUT ...
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IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 ELECTRICAL CHARACTERISTICS (Commercial 3.3V ± 0.3V 0°C to +70°C; Industrial Symbol Parameter f Clock ...
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IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18 FUNCTIONAL DESCRIPTION TIMING MODES: IDT STANDARD VS FIRST WORD FALL THROUGH (FWFT) MODE The IDT72V805/72V815/72V825/72V835/72V845 support two different timing modes of operation. ...
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IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18 normal read/write operation. When the LD pin and WEN are again set LOW, the next offset register in sequence is written. The ...
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IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18 TABLE 3 — TRUTH TABLE FOR CONFIGURATION AT RESET FL RXI WXI EF/ Single Register-Buffered Empty Flag 0 0 ...
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IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18 SIGNAL DESCRIPTIONS INPUTS: DATA IN (D0 - D17) Data inputs for 18-bit wide data. CONTROLS: RESET (RSA/RSB) Reset is accomplished whenever the ...
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IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18 OUTPUT ENABLE (OEA/OEB) When Output Enable (OEA/OEB) is enabled (LOW), the parallel output buffers receive data from the output register. When OE ...
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IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18 WRITE EXPANSION OUT/HALF-FULL FLAG (WXOA/HFA, WXOB/HFB) This is a dual-purpose output. In the Single Device and Width Expansion mode, when Write Expansion ...
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IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 REN, WEN, LD (1) FL, RXI, WXI (2) RCLK, WCLK FF/IR EF/OR PAF, WXO/ HF, RXO PAE ...
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IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18 RCLK t ENS REN OLZ OE WCLK WEN NOTES: is the minimum time between a ...
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IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 WRITE WCLK (1) t SKEW1 WEN RCLK t t ENS ENH REN OE LOW t ...
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IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 CLK t t CLKH CLKL WCLK t ENS LD t ENS WEN — PAE OFFSET Figure ...
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IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 CLKH WCLK WEN PAF words in FIFO RCLK REN NOTES PAF offset. 2. ...
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IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18 WCLK WXO t ENS WEN NOTE: 1. Write to Last Physical Location. RCLK RXO t ENS REN NOTE: 1. Read from Last ...
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IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18 COMMERCIAL AND INDUSTRIAL 18 TEMPERATURE RANGES FEBRUARY 11, 2009 ...
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IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18 COMMERCIAL AND INDUSTRIAL 19 TEMPERATURE RANGES FEBRUARY 11, 2009 ...
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IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 CLKH CLKL WCLK t ENH t ENS WEN PAE n words in FIFO ( 1words in FIFO ...
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IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t ENH t ENS REN OE LOW ...
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IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18 RCLK t t ENH ENS REN t REF OLZ WCLK ...
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IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18 OPERATING CONFIGURATIONS SINGLE DEVICE CONFIGURATION Each of the two FIFOs contained in a single IDT72V805/72V815/ 72V825/72V835/72V845 may be used as a stand-alone ...
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IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18 DEPTH EXPANSION CONFIGURATION — DAISY CHAIN TECHNIQUE (WITH PROGRAMMABLE FLAGS) These devices can easily be adapted to applications requiring more than 256/512/1,024/2,048/4,096 ...
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IDT72V805/72V815/72V825/72V835/72V845 3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18 For an empty expansion configuration, the amount of time it takes for OR of the last FIFO in the chain to go ...
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ORDERING INFORMATION XXXXX X XX Device Type Power Speed NOTES: 1. Industrial temperature range product for the 15ns speed grade is available as a standard device. 2. Green parts are available. For specific speeds and packages contact your sales office. ...