AD8191A-EVALZ Analog Devices, AD8191A-EVALZ Datasheet
AD8191A-EVALZ
Related parts for AD8191A-EVALZ
AD8191A-EVALZ Summary of contents
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... Outputs can be set to a high impedance state to reduce the power dissipation and/or to allow the construction of larger arrays using the wire-OR technique. The AD8191A is provided in a 100-lead LQFP, Pb-free, surface- mount package specified to operate over the −40°C to +85°C temperature range. ...
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... AD8191A TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Typical Application........................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 Maximum Power Dissipation ..................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 13 Introduction ................................................................................ 13 Input Channels............................................................................ 13 Output Channels ........................................................................ 13 Auxiliary Switch ...
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... Outputs enabled, maximum pre-emphasis 4 Input termination on Output termination on, no pre-emphasis Output termination on, maximum pre-emphasis Outputs disabled Outputs enabled, no pre-emphasis Outputs enabled, maximum pre-emphasis High speed switching register: HS_CH All other configuration registers Rev Page AD8191A Min Typ Max Unit 1.65 Gbps − (p-p) ...
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... Differential interpair skew is measured between the TMDS pairs of a single link. 2 AD8191A output meets the transmitter eye diagram as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.2a. 3 Cable output meets the receiver eye diagram mask as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.2a. ...
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... MAXIMUM POWER DISSIPATION AVCC − 1.4 V < V < IN AVCC + 0.6 V The maximum power that can be safely dissipated by the 2.0 V AD8191A is limited by the associated rise in junction DVEE − 0.3 V < V < IN temperature. The maximum safe junction temperature for AMUXVCC + 0.6 V plastic encapsulated devices is determined by the glass DVEE − 0.3 V < V < ...
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... IP_B2 11 IN_B3 12 IP_B3 14 IN_A0 15 IP_A0 17 IN_A1 18 IP_A1 20 IN_A2 AD8191A TOP VIEW (Not to Scale) Figure 3. Pin Configuration 1 Type Description Power Positive Analog Supply. 3.3 V nominal High Speed Input Complement High Speed Input. Power Negative Analog Supply nominal High Speed Input Complement. ...
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... High Speed Equalization Selection Parallel Interface. LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. Power Positive Auxiliary Multiplexer Supply typical. LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. Rev Page AD8191A ...
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... AD8191A Pin No. Mnemonic 87 AUX_COM3 88 AUX_COM2 89 AUX_COM1 90 AUX_COM0 91 AUX_B3 92 AUX_B2 93 AUX_B1 94 AUX_B0 96 AUX_A3 97 AUX_A2 98 AUX_A1 99 AUX_A0 100 PP_OTO high speed low speed input output. 1 Type Description LS I/O Low Speed Common Input/Output. LS I/O Low Speed Common Input/Output. LS I/O Low Speed Common Input/Output. LS I/O Low Speed Common Input/Output. ...
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... Figure 7. Rx Eye Diagram at TP3 (Cable = 2 meters, 30 AWG) Figure 8. Rx Eye Diagram at TP3 (Cable = 20 meters, 24 AWG) Rev Page − 1, data rate = 1.65 Gbps, unless AD8191A SERIAL DATA EVALUATION ANALYZER BOARD SMA COAX CABLE TP2 TP3 0.125UI/DIV AT 1.65Gbps 0.125UI/DIV AT 1.65Gbps AD8191A ...
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... TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 2 otherwise noted. REFERENCE EYE DIAGRAM AT TP1 0.125UI/DIV AT 1.65Gbps Figure 10. Tx Eye Diagram at TP2 0.125UI/DIV AT 1.65Gbps Figure 11. Tx Eye Diagram at TP2 AD8191A DIGITAL EVALUATION PATTERN BOARD GENERATOR SMA COAX CABLE ...
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... MAX PE 480p, PE OFF 0.1 480p, MAX HDMI CABLE LENGTH (m) 800 600 400 200 0 0 0.2 0.4 0.6 0.8 1.0 1.2 DATA RATE (Gbps) Figure 18. Eye Height vs. Data Rate 800 700 600 500 400 300 200 100 0 3.0 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) Figure 19. Eye Height vs. Supply Voltage AD8191A 20 25 1.4 1.6 1.8 3.5 3.6 ...
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... AD8191A T = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, AVEE = 0 V, DVEE = 0 V, differential input A swing = 1000 mV, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, pattern = PRBS 2 otherwise noted (p- (rms 0.2 0.4 0.6 0.8 1.0 1.2 DIFFERENTIAL INPUT SWING (mV) Figure 20. Jitter vs. Differential Input Swing ...
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... THEORY OF OPERATION INTRODUCTION The primary function of the AD8191A is to switch one of four (HDMI or DVI) single-link sources to one output. Each HDMI/ DVI link consists of four differential, high speed channels and four auxiliary single-ended, low speed control signals. The high speed channels include a data-word clock and three transition minimized differential signaling (TMDS) data channels running at 10× ...
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... AUX Figure 27. Auxiliary Channel Simplified Schematic, AUX_A0 to AUX_COM0 Routing Example When turning off the AD8191A, care needs to be taken with the AMUXVCC supply to ensure that the auxiliary multiplexer pins remain in a high impedance state. A scenario that illustrates this requirement is one where the auxiliary multiplexer is used to switch the display data channel (DDC) bus ...
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... I2C_SDA line low). 2. Send the AD8191A part address (seven bits). The upper four bits of the AD8191A part address are the static value [1001] and the three LSBs are set by Input Pin I2C_ADDR2, Input Pin I2C_ADDR1, and Input Pin I2C_ADDR0 (LSB). ...
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... Pin I2C_ADDR0 (LSB). This transfer should be MSB first. 9. Send the read indicator bit (1). 10. Wait for the AD8191A to acknowledge the request. 11. The AD8191A serially transfers the data (eight bits) held in the register indicated by the address set in Step 5. This data is sent MSB first. 12. Acknowledge the data from the AD8191A. ...
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... Table 1. Setting these pins updates the parallel control interface registers, as listed in Table 18. Following a reset, the AD8191A can be controlled through the parallel control interface until the first serial control event occurs. As soon as any serial control event ...
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... The serial interface configuration registers can be read and written using the I The least significant bits of the AD8191A I 3.3 V (Logic (Logic 0). As soon as the serial control interface is used, the parallel control interface is disabled until the AD8191A is reset, as described in the Serial Control Interface section. ...
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... Select Bit (For All Channels) Table 16. TX_PTO Description TX_PTO Description 0 Output termination off 1 Output termination on TX_OCL: High Speed (TMDS) Output Current Level Select Bit (For All Channels) Table 17. TX_OCL Description TX_OCL Description 0 Output current set Output current set Rev Page AD8191A ...
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... AD8191A PARALLEL INTERFACE CONFIGURATION REGISTERS The parallel interface configuration registers can be directly set using the PP_EN, PP_CH[1:0], PP_EQ, PP_PRE[1:0], PP_OTO, and PP_OCL pins. This interface is only accessible after the part is reset and before any registers are accessed using the serial control interface. ...
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... Table 24. PP_OTO Description PP_OTO Description 0 Output termination off 1 Output termination on PP_OCL: High Speed (TMDS) Output Current Level Select Bit (For All TMDS Channels) Table 25. TX_OCL Description PP_OCL Description 0 Output current set Output current set Rev Page AD8191A ...
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... AD8191A APPLICATIONS INFORMATION Figure 31. Layout of the TMDS Traces on the AD8191A Evaluation Board (Only Top Signal Routing Layer is Shown) The AD8191A is an HDMI/DVI switch featuring equalized TMDS inputs and pre-emphasized TMDS outputs intended for use as a 4:1 switch in systems with long cable runs on both the input and/or the output and is fully HDMI 1 ...
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... PCB layout. Regardless of the data being carried on a specific TMDS channel, or whether the TMDS line is at the input or the output of the AD8191A, all four high speed signals should be routed on a PCB in accordance with the same RF layout guidelines. ...
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... For example, interlayer vias can be used to route the AD8191A TMDS outputs on multiple layers of the PCB without severely degrading the quality of the output signal. Rev Page ...
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... SDA and SCL (serial data and serial clock, respectively). These four signals can be switched through the auxiliary bus of the AD8191A and do not need to be routed with the same strict considerations as the high speed TMDS signals. In general sufficient to route each auxiliary signal as a single-ended trace ...
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... Figure 34. Figure 34. Recommended Pad Outline for Bypass Capacitors In applications where the AD8191A is powered by a single 3.3 V supply recommended to use two reference supply planes and bypass the 3.3 V reference plane to the ground reference plane with one 220 pF capacitor, one 1000 pF capacitor, two 0.01 μ ...
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... OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range 1 AD8191AASTZ −40°C to +85°C 1 AD8191AASTZ-RL −40°C to +85°C 1 AD8191A-EVALZ RoHS Compliant Part. 16.20 16.00 SQ 1.60 MAX 15.80 0.75 100 1 0.60 0.45 PIN 1 TOP VIEW (PINS DOWN) 0.20 0.09 7° 3.5° 25 0° 26 0.08 COPLANARITY VIEW A ...
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... AD8191A NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips Patent Rights to use these components system, provided that the system conforms to the I C Standard Specification as defined by Philips. ...