LM1236 National Semiconductor Corporation, LM1236 Datasheet

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LM1236

Manufacturer Part Number
LM1236
Description
150 Mhz I2c Compatible Rgb Preamplifier With Internal 254 Character Osd Rom, 512 Character Ram And 4 Dacs
Manufacturer
National Semiconductor Corporation
Datasheet

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© 2005 National Semiconductor Corporation
LM1236
150 MHz I
254 Character OSD ROM, 512 Character RAM and 4
DACs
General Description
The LM1236 pre-amp is an integrated CMOS CRT preamp.
It has an I
the parameters necessary to directly setup and adjust the
gain and contrast in the CRT display. Brightness and bias
can be controlled through the DAC outputs, which are well
matched to the LM2479 and LM2480 integrated bias clamp
ICs. The LM1236 preamp is also designed to be compatible
with the LM246x high gain driver family.
Black level clamping of the video signal is carried out directly
on the AC coupled input signal into the high impedance
preamplifier input, thus eliminating the need for additional
clamp capacitors. Horizontal and vertical blanking of the
outputs is provided. Vertical blanking is optional and its
duration is register programmable.
The IC is packaged in an industry standard 24-lead DIP
molded plastic package.
Features
n Internal 254 character OSD ROM usable as either (a)
n Internal 512 character RAM, which can be displayed as
n Enhanced I
190 2-color plus 64 4-color characters, (b) 318 2-color
characters, or (c) some combination in between
one single or two independent windows
to allow versatile Page RAM access
2
C compatible interface which allows control of all
2
C compatible microcontroller interface
2
C Compatible RGB Preamplifier with Internal
DS200757
n OSD Window Fade In/Fade Out
n OSD Half Tone Transparency
n OSD override allows OSD messages to override video
n 4 DAC outputs (8-bit resolution) for bus controlled CRT
n Spot killer which blanks the video outputs when V
n Suitable for use with discrete or integrated clamp, with
n 4-Bit Programmable start position for internal
n Horizontal blanking and OSD synchronization directly
n Vertical blanking and OSD synchronization directly from
n Power Saving Mode with 65% power reduction
n Matched to LM246x driver and LM2479/80 bias IC’s
Applications
n Low end 15" and 17" bus controlled monitors with OSD
n 1024x768 displays up to 85 Hz requiring OSD capability
n Very low cost systems with LM246x driver
and the use of burn-in screens with no video output.
bias and brightness
falls below the specified threshold
software configurable brightness mixer
Horizontal Blanking
from deflection signals. The blanking can be disabled, if
desired.
deflection signals. The blanking width is register
programmable and can be disabled, if desired.
PRELIMINARY
September 2003
www.national.com
CC

Related parts for LM1236

LM1236 Summary of contents

Page 1

... DAC outputs, which are well matched to the LM2479 and LM2480 integrated bias clamp ICs. The LM1236 preamp is also designed to be compatible with the LM246x high gain driver family. Black level clamping of the video signal is carried out directly ...

Page 2

... Internal Block Diagram www.national.com FIGURE 1. Order Number LM1236AAA/NA See NS Package Number N24D 2 20075701 ...

Page 3

Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage V , Pins 10 and 18 CC Peak Video DC Output Source Current (Any One Amp) Pins ...

Page 4

Video Signal Electrical Characteristics Unless otherwise noted 25˚ numbers refer to the definitions in Table 1 . See (Note 7) for Min and Max parameters and (Note 6) for Typicals. Symbol Parameter V TH ABL Control ...

Page 5

DAC Output Electrical Characteristics Unless otherwise noted 25˚ for Min and Max parameters and (Note 6) for Typicals. DAC parameters apply to all 4 DACs. Symbol Parameter V Min Output Voltage of DAC Min DAC V ...

Page 6

... Note 15: A minimum pulse width of 200 ns is the guaranteed minimum for a horizontal line of 15 kHz. This limit is guaranteed by design lower line rate is used then a longer clamp pulse may be required. Note 16: Adjust input frequency from 10 MHz (A Note 17: Once the spot killer has been activated, the LM1236 remains in the off state until V Hexadecimal and Binary Notation Hexadecimal numbers appear frequently throughout this document, representing slave and register addresses, and register values. These appear in the format “ ...

Page 7

... OSD intensity to the most pleasing level. ESD Protection The LM1236 features a 3.0 kV ESD protection level (see (Notes 4, 13)). This is provided by special internal circuitry which activates when the voltage at any pin goes beyond the supply rails by a preset amount. At that time, the protection is applied to all the pins, including SDA and SCL ...

Page 8

Typical Performance Characteristics FIGURE 2. Logic Horizontal Blanking FIGURE 3. Logic Vertical Blanking FIGURE 4. Deflection Horizonal Blanking www.national.com 25˚C unless otherwise specified CC A 20075702 FIGURE 5. Deflection Vertical Blanking 20075703 FIGURE 6. Logic ...

Page 9

... The PLL in the LM1236 has a maximum pixels per line setting significantly higher than that of the LM1247. The range for the LM1236 is from 704 to 1152 pixels per line, in increments of 64. The maximum OSD pixel frequency avail- able is 111 MHz. For example, if the horizontal scan rate is ...

Page 10

... OSD pixel frequency of 111 MHz. The maxi- mum number of vertical video lines that may be used is 1536 lines 2048x1536 display. The LM1236 has a PLL Auto feature, which will automatically select an internal PLL frequency range setting that will guarantee optimal OSD locking for any horizontal scan rate ...

Page 11

Pin Descriptions and Application Information Pin Pin Name No REF 4 Analog Input Ground 5 Blue Video In 6 Red Video In 7 Green Video In 8 Digital Ground 10 Digital PLL Filter 11 SDA ...

Page 12

Pin Descriptions and Application Information Pin Pin Name No. 12 SCL 13 DAC 4 Output 14 DAC 2 Output 15 DAC 3 Output 16 DAC 1 Output 17 Ground Green Output 20 Red Output 21 Blue ...

Page 13

Pin Descriptions and Application Information Pin Pin Name No. 23 CLAMP 24 H Flyback (Continued) Schematic This pin accepts either TTL or CMOS logic levels. The internal switching threshold is approximately one-half of V series resistor avoid overdriving ...

Page 14

Schematic Diagram FIGURE 9. LM123x/LM124x-LM246x Demo Board Schematic www.national.com 14 20075724 ...

Page 15

Schematic Diagram FIGURE 10. LM123x/LM124x-LM246x Demo Board Schematic (continued) 15 20075725 www.national.com ...

Page 16

PCB Layout FIGURE 11. LM123x/LM124x-LM246x Demo Board Layout www.national.com 16 20075726 ...

Page 17

Programmable Horizontal Blank The leading edge position of the internal horizontal blank can be programmed with respect to the horizontal flyback zero crossing leading edge in steps of 4 OSD pixels maximum of 16 steps as shown ...

Page 18

OSD Generator Operation PAGE OPERATION Figure 13 shows the block diagram of the OSD generator. OSD screens are created using any of the 256 predefined characters stored in the mask programmed ROM. Each character has a unique 8-bit code that ...

Page 19

OSD Generator Operation OSD VIDEO TIMING The OSD analog signal then goes to the switch, shown in Figure 14 and Figure 1 where the timing control switches from input video to OSD and back again as determined by CHARACTER CELL ...

Page 20

OSD Generator Operation FOUR COLOR FONT AS TWO 2-COLOR Using a 4 color character as two 2 color characters is achieved by careful assignment of the four colors. When two 2 color characters are combined, there will be four pixel ...

Page 21

OSD Generator Operation FIGURE 18. Displaying Each Character Individually ATTRIBUTE TABLES Each character has an attribute value assigned the page RAM. The attribute value is 4 bits wide, making each character entry in the page RAM 13 ...

Page 22

OSD Generator Operation OSD WINDOW FADE IN/ FADE OUT The OSD window can be opened and closed with a fade in/fade out effect. The interval for fading in and fading out the OSD window in the horizontal and vertical direction ...

Page 23

OSD Generator Operation FIGURE 20. On-Screen Effect of Button Boxes (Continued) FIGURE 19. Button Box Detail 20075736 FIGURE 21. Shadowing 23 20075734 20075735 www.national.com ...

Page 24

... LM1236 preamp associated with the ad- dress indicated by the two address bytes. Subsequent read data bytes will correspond to the next increment address locations. Data should only be read from the LM1236 when both OSD windows and the Fade In/ Fade Out are disabled. 24 ...

Page 25

... Microcontroller Interface LM1236 Address Map CHARACTER ROM Note that bit 0 of the Character Font Access Register, 0x8402, needs to be set read the 2-color fonts. In order to read the four-color fonts, two complete reads are needed. Set bit 0 of the Character Font Access Register, 0x8402 read the least significant plane and read the most significant plane ...

Page 26

... LM1236 Address Map Address Range 0x0000–0x2FFF 0x3000–0x3FFF 0x4000–0x7FFF DISPLAY PAGE RAM This address range (0x8000–0x81FF) contains the 512 characters, which comprise the displayable OSD screens. There must be at least one End-Of-Screen code (0x00) in this range to prevent unpredictable behavior. NOTE: To avoid any unpredictable behavior, this range should be cleared by writing bit 3 of the FRMCTRL1 Register, 0x8400, immediately after power up ...

Page 27

... LM1236 Address Map are used, one for 2-color characters, the other for 4-color characters. Each of the characters are stored in sequence in the Page RAM. Special codes are used between lines to show where oneline ends and the next begins, and also to allow blank (or ’ ...

Page 28

... TABLE 11. OSD Control Register Detail (Continued B[1: B[1: V_INTVL[3:0] TABLE 12. LM1236 Preamplifier Interface Registers DCF[1: HB_POS[3:0] PLL_ X CLMP AUTO X AID ...

Page 29

... ATT4C4n +4 ATT4C5n +5 ATT4C6n +6 ATT4C7n +7 (Continued) Address = 0x8440 + (N * 0x4 where Attribute number (0x0 ≤ N ≤ 0xF Attribute byte number (0x0 ≤ B ≤ 0x3) TABLE 13. LM1236 Two-Color Attribute Registers C0B[1:0] C1B[0] C1G[2: Address = 0x8500 + (N * 0x8 where Attribute number (0x0 ≤ N ≤ 0xF Attribute byte number (0x0 ≤ ...

Page 30

... ENHANCED PAGE RAM ADDRESS MODES Since the Page RAM in the LM1236 is 12 bits wide, usually two bytes of Page RAM information has to be sent to every location. To avoid this, the LM1236 addressing control system has 3 additional addressing modes offering increased flexibility that may be helpful in sending data to the Page RAM. Some of the left over bits in the Attribute byte are employed as data control bits to select the desired addressing mode as shown in Table 16 . This is identified as the first byte sent in a write operation or the Page RAM’ ...

Page 31

Building Display Pages X When bits 6–5 are 0, the 4-bit attribute code will be automatically applied to all the character codes transmitted after this attribute byte the LM1237 and LM1247. This mode is useful for sending character ...

Page 32

Building Display Pages Control Register Definitions OSD INTERFACE REGISTERS Frame Control Register 1: halftone HTD Bit 0 On-Screen Display Enable. The On-Screen Display will be disabled when this bit is a zero. When this bit is a one the On-Screen ...

Page 33

Control Register Definitions Character Font Access Register: X Bit 0 This is the Color Bit Plane Selector. This bit must be set read or write a two-color attribute from the range 0x0000 to 0x2FFF. When reading or ...

Page 34

Control Register Definitions CHSDWCTRLB1 (0x840A) Reserved Bits 8–0 These registers determine the heavy button box lowlight, shading or shadow color. Bits 15–9 Reserved. These bits should be set to zero. ROM Signature Control Register: X ...

Page 35

... SL code for the first line of Display Window 1. This register is new for the LM1236 and allows Window 1 to start anywhere in the Page RAM rather than just at 0x8000. Note that the address this points to in Page RAM must always contain the SL code for the first line of the window. Bits 15– ...

Page 36

Control Register Definitions Bits 15–9 These bits are reserved and should be set to zero. Display Window 2 Column Width: COLWIDTH2B3 (0x841F) COLWIDTH2B1 (0x841D) Bits 31–0 These are the Display Window 2 Column Width 2x Enable Bits. These thirty-two bits ...

Page 37

Pre-Amplifier Interface Registers Bits 6–0 This register determines the gain of the red video channel. This affects only the red channel whereas the contrast register (0x8433) affects all channels. Bit 7 Reserved and should be set to zero. Contrast Control: ...

Page 38

... Bit 4 Reserved and should be set to zero. Bit 5 This is the Clamp Polarity bit. When set the LM1236 expects a positive going clamp pulse. When set the expected pulse is negative going. Bit 6 When this bit is set, the PLL Auto Mode will automatically determine the optimum frequency range of the Phase Locked Loop ...

Page 39

Pre-Amplifier Interface Registers Software Reset and Test Control: Res’d X AID Bit 0 When this bit all registers except this one are loaded with their default values. All operations are aborted, except data transfers in progress on ...

Page 40

Attribute Table and Enhanced Features TABLE 25. Enhanced Feature Descriptions (Continued) Bits 21–18 1100b 1101b 1110b 1111b FOUR COLOR ATTRIBUTE FORMAT The address range for an attribute number, 0 ≤ n ≤ 15, is provided in Table 26 . ATT4C7n ...

Page 41

Attribute Table and Enhanced Features (Continued) BUTTON BOX FORMATION The value of the most significant Enhanced Feature Bit (EFB3) determines when to draw the left, right, bottom and top sides of a Box. EFB1 denotes whether a box is raised ...

Page 42

... Attribute Table and Enhanced Features (Continued) Evaluation Character Fonts The character font for evaluation of the LM1236 is shown in Figure 26 . The actual font will depend on customer customi- zation requirements. www.national.com FIGURE 26. ROM Character Font 42 20075744 ...

Page 43

... English www.national.com Français Tel: +33 ( 8790 24-Lead DIP Molded Plastic Package Order Number LM1236AAA/NA NS Package Number N24D 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system affect its safety or effectiveness ...

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