LM1236 National Semiconductor Corporation, LM1236 Datasheet - Page 9

• Manufacturer Part Number: LM1236
• Description: 150 Mhz I2c Compatible Rgb Preamplifier With Internal 254 Character Osd Rom, 512 Character Ram And 4 Dacs
• Manufacturer: National Semiconductor Corporation

Typical Performance Characteristics
SYSTEM INTERFACE SIGNALS
The Horizontal and Vertical Blanking and the Clamping input
signals are important for proper functionality of the LM1236.
Both blanking inputs must be present for OSD synchroniza-
tion. In addition, the Horizontal blanking input also assists in
setting the proper cathode black level, along with the Clamp-
ing pulse. The Vertical blanking input initiates a blanking
level at the LM1236 outputs which is programmable from 3
to 127 lines (we recommend at least 10). The start position
of the internal Horizontal blanking pulse is programmable
from 0 to 64 pixels ahead of the start position of the Hori-
zontal flyback input. Both horizontal and vertical blanking
can be individually disabled, if desired.
Figure 2 and Figure 3 show the case where the Horizontal
and Vertical inputs are logic levels. Figure 2 shows the
smaller pin 24 voltage superimposed on the horizontal
blanking pulse input to the neck board with R
C
about 1V when the pin is sinking current. Figure 3 shows the
smaller pin 1 voltage superimposed on the vertical blanking
input to the neck board with C
These component values correspond to the application cir-
cuit of Figure 9.
Figures 4, 5 show the case where the horizontal and vertical
inputs are from deflection. Figure 4 shows the pin 24 voltage
which is derived from a horizontal flyback pulse of 35V peak
to peak with R
the pin 1 voltage which is derived from a vertical flyback
pulse of 55V peak to peak with C
Figure 6 shows the pin 23 clamp input voltage superimposed
on the neck board clamp logic input pulse. R
should be chosen to limit the pin 23 voltage to about 2.5V
peak to peak. This corresponds to the application circuit
given in Figure 9.
17
= 0.1 µF. Note where the voltage at pin 24 is clamped to
H
= 8.2K and C
17
4
4
jumpered. Figure 5 shows
jumpered and R
= 1500 pF and R
FIGURE 8. ABL Gain Reduction Curve
H
31
= 4.7k and
= 1k and
V
V
= 120k.
= 4.7k.
V
CC
9
= 5V, T
CATHODE RESPONSE
Figure 7 shows the response at the red cathode for the
application circuit in Figures 9, 10. The input video risetime is
1.5 ns. The resulting leading edge has a 7.1 ns risetime and
a 7.6% overshoot, while the trailing edge has a 7.1 ns
risetime and a 6.9% overshoot with an LM2467 driver.
ABL GAIN REDUCTION
The ABL function reduces the contrast level of the LM1236
as the voltage on pin 22 is lowered from V
Figure 8 shows the amount of gain reduction as the voltage
is lowered from V
until V
increases. Many system designs will require about 3 dB to
5 dB of gain reduction in full beam limiting. Additional attenu-
ation is possible, and can be used in special circumstances.
However, in this case, video performance such as video
linearity and tracking between channels will tend to depart
from normal specifications.
OSD PHASE LOCKED LOOP
The PLL in the LM1236 has a maximum pixels per line
setting significantly higher than that of the LM1247. The
range for the LM1236 is from 704 to 1152 pixels per line, in
increments of 64. The maximum OSD pixel frequency avail-
able is 111 MHz. For example, if the horizontal scan rate is
106kHz, 1024 pixels per line would be acceptable to use,
since the OSD pixel frequency is:
22
A
= 25˚C unless otherwise specified (Continued)
reaches the knee around 3.7V, where the slope
20075708
Horizontal Scan Rate X PPL =
106kHz X 1024 = 108.5 MHz
CC
(5.0V) to 2V. The gain reduction is small
CC
to around 2V.
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