LM1236 National Semiconductor Corporation, LM1236 Datasheet - Page 10

• Manufacturer Part Number: LM1236
• Description: 150 Mhz I2c Compatible Rgb Preamplifier With Internal 254 Character Osd Rom, 512 Character Ram And 4 Dacs
• Manufacturer: National Semiconductor Corporation

www.national.com
Pin
No.
Typical Performance Characteristics
If 1152 pixels per line is being used, the horizontal scan rate
would have to be lower than 106 kHz in order to not exceed
the maximum OSD pixel frequency of 111 MHz. The maxi-
mum number of vertical video lines that may be used is 1536
lines as in a 2048x1536 display. The LM1236 has a PLL
Auto feature, which will automatically select an internal PLL
frequency range setting that will guarantee optimal OSD
locking for any horizontal scan rate. This offers improved
PLL performance and eliminates the need for PLL register
settings determined by the user. To initialize the PLL Auto
feature, set bits, 0x843E[1:0] to 0 for pre-calibration, which
takes one vertical scan period to complete, and must be
done while the video is blanked. Subsequently, set
0x843E[6] to 1, which must also be done while the video is
blanked. Table 3 shows the recommended horizontal scan
rate ranges (in kHz) for each pixels per line register setting,
0x8401[7:5]. These ranges are recommended for chip am-
bient temperatures of 0
PLL filter values are 6.2kohms, 0.01uF, and 1000pF as
shown in the schematic. While the OSD PLL will lock for
other register combinations and at scan rates outside these
Pin Descriptions and Application Information
1
2
PLL Auto
V
Pin Name
REF
V Flyback
Bypass
25 - 110
PPL=0
o
C to 70
25 - 110
o
PPL=1
C, and the recommended
TABLE 3. OSD Register Recommendations
Schematic
25 - 110
PPL=2
25 - 110
PPL=3
V
10
CC
= 5V, T
ranges, the performance of the loop will be improved if these
recommendations are followed.
PLL Auto Mode Initialization Sequence
• Blank video
• In PLL manual mode, set PLL range (0x843E[1:0]) to 0
• Wait for at least one vertical period or vertical sync pulse
• Set 0x843E[6] to 1 to activate the Auto mode
• Wait for at least one vertical period or vertical sync pulse
• Unblank video
This Sequence must be done by the microcontroller at sys-
tem power up, as well as each time there is a horizontal line
rate change from the video source, for the PLL Auto mode to
function properly.
to pass
to pass
A
25 - 110
PPL=4
= 25˚C unless otherwise specified (Continued)
Required for OSD synchronization and is also
used for vertical blanking of the video outputs.
The actual switching threshold is about 35% of
V
but for flyback inputs, an AC coupled
differentiator is recommended, where R
enough to prevent the voltage at pin 1 from
exceeding V
be small enough to flatten the vertical rate ramp
at pin 1. C
Provides filtering for the internal voltage which
sets the internal bias current in conjunction with
R
proper filtering. This capacitor should be placed
as close to pin 2 and the pin 4 ground return as
possible.
CC
EXT
. For logic level inputs C
. A minimum of 0.1 µF is recommended for
25 - 108
PPL=5
24
CC
may be needed to reduce noise.
or going below GND. C
Description
25 - 102
PPL=6
4
can be a jumper,
25 - 96
PPL=7
4
V
should
is large