LM3S8930 Luminary Micro, Inc, LM3S8930 Datasheet - Page 113
LM3S8930
Manufacturer Part Number
LM3S8930
Description
Lm3s8930 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S8930.pdf
(526 pages)
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Reset
Reset
Type
Type
Software Reset Control 0 (SRCR0)
Base 0x400F.E000
Offset 0x040
Type R/W, reset 0x00000000
July 25, 2008
Bit/Field
31:26
23:7
5:4
2:0
25
24
6
3
RO
RO
31
15
0
0
Register 27: Software Reset Control 0 (SRCR0), offset 0x040
Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register.
RO
RO
30
14
0
0
reserved
reserved
reserved
reserved
RO
RO
29
13
0
0
Name
CAN1
CAN0
WDT
reserved
HIB
RO
RO
28
12
0
0
reserved
RO
RO
27
11
0
0
Type
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
26
10
0
0
Reset
CAN1
R/W
RO
25
0
9
0
0
0
0
0
0
0
0
0
Preliminary
CAN0
R/W
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
CAN1 Reset Control
Reset control for CAN unit 1.
CAN0 Reset Control
Reset control for CAN unit 0.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
HIB Reset Control
Reset control for the Hibernation module.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
WDT Reset Control
Reset control for Watchdog unit.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RO
RO
23
0
7
0
R/W
HIB
RO
22
0
6
0
RO
RO
21
0
5
0
reserved
RO
RO
20
0
4
0
reserved
LM3S8930 Microcontroller
WDT
R/W
RO
19
0
3
0
RO
RO
18
0
2
0
reserved
RO
RO
17
0
1
0
RO
RO
16
0
0
0
113
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