LM3S8930 Luminary Micro, Inc, LM3S8930 Datasheet - Page 476

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LM3S8930

Manufacturer Part Number
LM3S8930
Description
Lm3s8930 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet

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Signal Tables
476
Pin Number
K12
K11
L10
L12
L11
M1
M2
M3
M4
M5
M6
M7
M8
M9
L1
L2
L3
L4
L5
L6
L7
L8
L9
Pin Name
SSI0Fss
SSI0Clk
SSI0Rx
SSI0Tx
CAN1Rx
XOSC0
XOSC1
U0Rx
CCP1
RXIN
TXON
MDIO
OSC0
VBAT
U0Tx
RXIP
TXOP
PA0
PA3
PA4
PA6
GND
PA1
PA2
PA5
PA7
PF0
NC
NC
NC
NC
Preliminary
Pin Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
-
-
-
-
-
-
I
I
I
I
I
I
I
Buffer Type
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Power
Power
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
-
-
-
-
Description
Hibernation Module oscillator crystal input or
an external clock reference input. Note that
this is either a 4.19-MHz crystal or a
32.768-kHz oscillator for the Hibernation
Module RTC. See the CLKSEL bit in the
HIBCTL register.
Hibernation Module oscillator crystal output.
No connect. Leave the pin electrically
unconnected/isolated.
No connect. Leave the pin electrically
unconnected/isolated.
GPIO port A bit 0
UART module 0 receive. When in IrDA mode,
this signal has IrDA modulation.
GPIO port A bit 3
SSI module 0 frame
GPIO port A bit 4
SSI module 0 receive
GPIO port A bit 6
Capture/Compare/PWM 1
RXIN of the Ethernet PHY
TXON of the Ethernet PHY
MDIO of the Ethernet PHY
Ground reference for logic and I/O pins.
Main oscillator crystal input or an external
clock reference input.
Power source for the Hibernation Module. It
is normally connected to the positive terminal
of a battery and serves as the battery
backup/Hibernation Module power-source
supply.
No connect. Leave the pin electrically
unconnected/isolated.
No connect. Leave the pin electrically
unconnected/isolated.
GPIO port A bit 1
UART module 0 transmit. When in IrDA mode,
this signal has IrDA modulation.
GPIO port A bit 2
SSI module 0 clock
GPIO port A bit 5
SSI module 0 transmit
GPIO port A bit 7
RXIP of the Ethernet PHY
TXOP of the Ethernet PHY
GPIO port F bit 0
CAN module 1 receive
July 25, 2008

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