LM3S8930 Luminary Micro, Inc, LM3S8930 Datasheet - Page 8

• Manufacturer Part Number: LM3S8930
• Description: Lm3s8930 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
List of Figures
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 6-1.
Figure 6-2.
Figure 6-3.
Figure 7-1.
Figure 7-2.
Figure 7-3.
Figure 8-1.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 10-1.
Figure 10-2.
Figure 10-3.
Figure 10-4.
Figure 11-1.
Figure 12-1.
Figure 12-2.
Figure 12-3.
Figure 13-1.
Figure 13-2.
Figure 13-3.
Figure 13-4.
Figure 13-5.
Figure 13-6.
Figure 13-7.
Figure 13-8.
Figure 13-9.
Figure 13-10. MICROWIRE Frame Format (Single Frame) .................................................................... 310
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 311
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 311
Figure 14-1.
Figure 14-2.
Figure 14-3.
Figure 14-4.
Figure 14-5.
Figure 14-6.
Figure 14-7.
8
Stellaris
CPU Block Diagram ......................................................................................................... 37
TPIU Block Diagram ........................................................................................................ 38
JTAG Module Block Diagram ............................................................................................ 48
Test Access Port State Machine ....................................................................................... 51
IDCODE Register Format ................................................................................................. 56
BYPASS Register Format ................................................................................................ 57
Boundary Scan Register Format ....................................................................................... 57
External Circuitry to Extend Reset .................................................................................... 59
Power Architecture .......................................................................................................... 62
Main Clock Tree .............................................................................................................. 64
Hibernation Module Block Diagram ................................................................................. 118
Clock Source Using Crystal ............................................................................................ 119
Clock Source Using Dedicated Oscillator ......................................................................... 120
Flash Block Diagram ...................................................................................................... 137
GPIO Port Block Diagram ............................................................................................... 162
GPIODATA Write Example ............................................................................................. 163
GPIODATA Read Example ............................................................................................. 163
GPTM Module Block Diagram ........................................................................................ 203
16-Bit Input Edge Count Mode Example .......................................................................... 207
16-Bit Input Edge Time Mode Example ........................................................................... 208
16-Bit PWM Mode Example ............................................................................................ 209
WDT Module Block Diagram .......................................................................................... 238
UART Module Block Diagram ......................................................................................... 262
UART Character Frame ................................................................................................. 263
IrDA Data Modulation ..................................................................................................... 265
SSI Module Block Diagram ............................................................................................. 302
TI Synchronous Serial Frame Format (Single Transfer) .................................................... 305
TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 305
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 306
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 306
Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 307
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 308
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 308
Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 309
I
I
START and STOP Conditions ......................................................................................... 340
Complete Data Transfer with a 7-Bit Address ................................................................... 341
R/S Bit in First Byte ........................................................................................................ 341
Data Validity During Bit Transfer on the I
Master Single SEND ...................................................................................................... 344
2
2
C Block Diagram ......................................................................................................... 339
C Bus Configuration .................................................................................................... 340
®
8000 Series High-Level Block Diagram ............................................................... 29
Preliminary
2
C Bus ............................................................... 341
July 25, 2008