LM3S8930 Luminary Micro, Inc, LM3S8930 Datasheet - Page 5

• Manufacturer Part Number: LM3S8930
• Description: Lm3s8930 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

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10.1
10.2
10.2.1 GPTM Reset Conditions .......................................................................................................... 204
10.2.2 32-Bit Timer Operating Modes .................................................................................................. 204
10.2.3 16-Bit Timer Operating Modes .................................................................................................. 205
10.3
10.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 209
10.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 210
10.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 210
10.3.4 16-Bit Input Edge Count Mode ................................................................................................. 211
10.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 211
10.3.6 16-Bit PWM Mode ................................................................................................................... 212
10.4
10.5
11
11.1
11.2
11.3
11.4
11.5
12
12.1
12.2
12.2.1 Transmit/Receive Logic ........................................................................................................... 262
12.2.2 Baud-Rate Generation ............................................................................................................. 263
12.2.3 Data Transmission .................................................................................................................. 263
12.2.4 Serial IR (SIR) ......................................................................................................................... 264
12.2.5 FIFO Operation ....................................................................................................................... 265
12.2.6 Interrupts ................................................................................................................................ 265
12.2.7 Loopback Operation ................................................................................................................ 266
12.2.8 IrDA SIR block ........................................................................................................................ 266
12.3
12.4
12.5
13
13.1
13.2
13.2.1 Bit Rate Generation ................................................................................................................. 303
13.2.2 FIFO Operation ....................................................................................................................... 303
13.2.3 Interrupts ................................................................................................................................ 303
13.2.4 Frame Formats ....................................................................................................................... 304
13.3
13.4
13.5
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14.1
July 25, 2008
General-Purpose Timers ................................................................................................. 202
Block Diagram ........................................................................................................................ 202
Functional Description ............................................................................................................. 203
Initialization and Configuration ................................................................................................. 209
Register Map .......................................................................................................................... 212
Register Descriptions .............................................................................................................. 213
Watchdog Timer ............................................................................................................... 238
Block Diagram ........................................................................................................................ 238
Functional Description ............................................................................................................. 238
Initialization and Configuration ................................................................................................. 239
Register Map .......................................................................................................................... 239
Register Descriptions .............................................................................................................. 240
Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 261
Block Diagram ........................................................................................................................ 262
Functional Description ............................................................................................................. 262
Initialization and Configuration ................................................................................................. 266
Register Map .......................................................................................................................... 267
Register Descriptions .............................................................................................................. 268
Synchronous Serial Interface (SSI) ................................................................................ 302
Block Diagram ........................................................................................................................ 302
Functional Description ............................................................................................................. 302
Initialization and Configuration ................................................................................................. 311
Register Map .......................................................................................................................... 312
Register Descriptions .............................................................................................................. 313
Inter-Integrated Circuit (I
Block Diagram ........................................................................................................................ 339
2
C) Interface ............................................................................ 339
Preliminary
LM3S8930 Microcontroller
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