LM3S5652 Luminary Micro, Inc, LM3S5652 Datasheet - Page 12

• Manufacturer Part Number: LM3S5652
• Description: Lm3s5652 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
List of Tables
Table 1.
Table 3-1.
Table 4-1.
Table 4-2.
Table 5-1.
Table 5-2.
Table 6-1.
Table 7-1.
Table 8-1.
Table 8-2.
Table 8-3.
Table 9-1.
Table 9-2.
Table 9-3.
Table 9-4.
Table 9-5.
Table 9-6.
Table 9-7.
Table 9-8.
Table 9-9.
Table 9-10.
Table 9-11.
Table 9-12.
Table 9-13.
Table 10-1.
Table 10-2.
Table 10-3.
Table 11-1.
Table 11-2.
Table 11-3.
Table 12-1.
Table 13-1.
Table 13-2.
Table 13-3.
Table 14-1.
Table 15-1.
Table 16-1.
Table 16-2.
Table 16-3.
Table 17-1.
Table 17-2.
Table 17-3.
Table 17-4.
Table 18-1.
Table 19-1.
Table 19-2.
12
Documentation Conventions ............................................................................................ 23
Memory Map ................................................................................................................... 48
Exception Types .............................................................................................................. 51
Interrupts ........................................................................................................................ 52
JTAG Port Pins Reset State ............................................................................................. 56
JTAG Instruction Register Commands ............................................................................... 61
System Control Register Map ........................................................................................... 75
Hibernation Module Register Map ................................................................................... 136
Flash Protection Policy Combinations ............................................................................. 153
Flash Resident Registers ............................................................................................... 154
Flash Register Map ........................................................................................................ 155
DMA Channel Assignments ............................................................................................ 182
Request Type Support ................................................................................................... 183
Control Structure Memory Map ....................................................................................... 184
Channel Control Structure .............................................................................................. 184
μDMA Read Example: 8-Bit Peripheral ............................................................................ 193
μDMA Interrupt Assignments .......................................................................................... 194
Channel Control Structure Offsets for Channel 30 ............................................................ 195
Channel Control Word Configuration for Memory Transfer Example .................................. 195
Channel Control Structure Offsets for Channel 7 .............................................................. 196
Channel Control Word Configuration for Peripheral Transmit Example .............................. 197
Primary and Alternate Channel Control Structure Offsets for Channel 8 ............................. 198
Channel Control Word Configuration for Peripheral Ping-Pong Receive Example ............... 199
μDMA Register Map ...................................................................................................... 200
GPIO Pad Configuration Examples ................................................................................. 246
GPIO Interrupt Configuration Example ............................................................................ 247
GPIO Register Map ....................................................................................................... 248
Available CCP Pins ........................................................................................................ 287
16-Bit Timer With Prescaler Configurations ..................................................................... 290
Timers Register Map ...................................................................................................... 296
Watchdog Timer Register Map ........................................................................................ 321
Samples and FIFO Depth of Sequencers ........................................................................ 344
Differential Sampling Pairs ............................................................................................. 346
ADC Register Map ......................................................................................................... 349
UART Register Map ....................................................................................................... 382
SSI Register Map .......................................................................................................... 429
Examples of I
Inter-Integrated Circuit (I
Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 474
Transmit Message Object Bit Settings ............................................................................. 495
Receive Message Object Bit Settings .............................................................................. 497
CAN Protocol Ranges .................................................................................................... 500
CAN Register Map ......................................................................................................... 503
Univeral Serial Bus (USB) Controller Register Map .......................................................... 545
Comparator 0 Operating Modes ...................................................................................... 624
Internal Reference Voltage and ACREFCTL Field Values ................................................. 625
2
C Master Timer Period versus Speed Mode ............................................... 460
2
C) Interface Register Map ......................................................... 469
Preliminary
June 02, 2008