LM3S5652 Luminary Micro, Inc, LM3S5652 Datasheet - Page 558

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LM3S5652

Manufacturer Part Number
LM3S5652
Description
Lm3s5652 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet

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Reset
Type
Univeral Serial Bus (USB) Controller
USBIE Host Mode
USB Interrupt Enable (USBIE)
Base 0x4005.0000
Offset 0x00B
Type R/W, reset 0x06
558
Host
Device
Bit/Field
VBUSERR
R/W
7
6
5
4
3
2
1
0
7
0
SESREQ
R/W
Register 8: USB Interrupt Enable (USBIE), offset 0x00B
USBIE is an 8-bit register that provides interrupt enable bits for each of the interrupts in USBIS. By
default, interrupt 1 and 2 are enabled.
6
0
DISCON
VBUSERR
R/W
RESUME
SESREQ
SUSPND
DISCON
5
0
RESET
CONN
Name
SOF
CONN
R/W
4
0
SOF
R/W
3
0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET
R/W
2
1
RESUME
R/W
Reset
1
1
0
0
0
0
0
1
1
0
SUSPND
Preliminary
R/W
0
0
Description
Enable VBUS Error Interrupt
Set by CPU to enable VBUSERR in USBIS.
Enable Session Request
Set by CPU to enable SESREQ in USBIS.
Enable Disconnect Interrupt
Set by CPU to enable DISCON in USBIS.
Enable Connect Interrupt
Set by CPU to enable CONN in USBIS.
Enable Start-of-Frame Interrupt
Set by CPU to enable SOF in USBIS.
Enable Reset Interrupt
Set by CPU to enable RESET in USBIS.
Enable Resume Interrupt
Set by CPU to enable RESUME in USBIS.
Enable Suspend Interrupt
Set by CPU to enable SUSPEND in USBIS.
June 02, 2008

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