LM3S300 Luminary Micro, Inc, LM3S300 Datasheet - Page 14

• Manufacturer Part Number: LM3S300
• Description: Lm3s300 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
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Inter-Integrated Circuit (I
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Analog Comparators ................................................................................................................... 328
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
14
SSI Status (SSISR), offset 0x00C ................................................................................... 273
SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 275
SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 276
SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 278
SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 279
SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 280
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 281
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 282
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 283
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 284
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 285
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 286
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 287
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 288
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 289
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 290
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 291
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 292
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 334
Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 335
Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 336
Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 337
Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 338
Analog Comparator Status 1 (ACSTAT1), offset 0x40 ....................................................... 338
Analog Comparator Status 2 (ACSTAT2), offset 0x60 ....................................................... 338
Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 339
Analog Comparator Control 1 (ACCTL1), offset 0x44 ....................................................... 339
Analog Comparator Control 2 (ACCTL2), offset 0x64 ...................................................... 339
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 307
C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 308
C Master Data (I2CMDR), offset 0x008 ......................................................................... 312
C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 313
C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 314
C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 315
C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 316
C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 317
C Master Configuration (I2CMCR), offset 0x020 ............................................................ 318
C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 320
C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 321
C Slave Data (I2CSDR), offset 0x008 ........................................................................... 323
C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 324
C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 325
C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 326
C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 327
2
C) Interface ........................................................................................ 293
Preliminary
June 04, 2008