LM3S300 Luminary Micro, Inc, LM3S300 Datasheet - Page 240

• Manufacturer Part Number: LM3S300
• Description: Lm3s300 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Universal Asynchronous Receivers/Transmitters (UARTs)
UART Raw Interrupt Status (UARTRIS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x03C
Type RO, reset 0x0000.000F
240
Bit/Field
31:11
3:0
10
RO
RO
9
8
7
6
5
4
31
15
0
0
RO
RO
Register 10: UART Raw Interrupt Status (UARTRIS), offset 0x03C
The UARTRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt. A write has no effect.
30
14
0
0
reserved
RO
RO
29
13
reserved
reserved
0
0
OERIS
BERIS
PERIS
RTRIS
RXRIS
FERIS
TXRIS
Name
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
OERIS
RO
RO
26
10
0
0
BERIS
RO
RO
Reset
25
0x00
0
9
0
0xF
0
0
0
0
0
0
0
Preliminary
PERIS
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Overrun Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
UART Break Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
UART Parity Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
UART Framing Error Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
UART Receive Time-Out Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
UART Transmit Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
UART Receive Raw Interrupt Status
Gives the raw interrupt state (prior to masking) of this interrupt.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
FERIS
RO
RO
23
0
7
0
RTRIS
RO
RO
22
0
6
0
TXRIS
RO
RO
21
0
5
0
RXRIS
RO
RO
20
0
4
0
RO
RO
19
0
3
1
RO
RO
18
0
2
1
reserved
RO
RO
17
0
1
1
June 04, 2008
RO
RO
16
0
0
1