LM3S300 Luminary Micro, Inc, LM3S300 Datasheet - Page 7

• Manufacturer Part Number: LM3S300
• Description: Lm3s300 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

List of Figures
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 6-1.
Figure 6-2.
Figure 7-1.
Figure 8-1.
Figure 8-2.
Figure 8-3.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 10-1.
Figure 11-1.
Figure 11-2.
Figure 12-1.
Figure 12-2.
Figure 12-3.
Figure 12-4.
Figure 12-5.
Figure 12-6.
Figure 12-7.
Figure 12-8.
Figure 12-9.
Figure 12-10. MICROWIRE Frame Format (Single Frame) .................................................................... 264
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 265
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 265
Figure 13-1.
Figure 13-2.
Figure 13-3.
Figure 13-4.
Figure 13-5.
Figure 13-6.
Figure 13-7.
Figure 13-8.
Figure 13-9.
Figure 13-10. Master Burst RECEIVE .................................................................................................. 301
Figure 13-11. Master Burst RECEIVE after Burst SEND ........................................................................ 302
Figure 13-12. Master Burst SEND after Burst RECEIVE ........................................................................ 303
June 04, 2008
Stellaris
CPU Block Diagram ......................................................................................................... 30
TPIU Block Diagram ........................................................................................................ 31
JTAG Module Block Diagram ............................................................................................ 40
Test Access Port State Machine ....................................................................................... 43
IDCODE Register Format ................................................................................................. 47
BYPASS Register Format ................................................................................................ 47
Boundary Scan Register Format ....................................................................................... 48
External Circuitry to Extend Reset .................................................................................... 50
Main Clock Tree .............................................................................................................. 53
Flash Block Diagram ...................................................................................................... 104
GPIO Port Block Diagram ............................................................................................... 121
GPIODATA Write Example ............................................................................................. 122
GPIODATA Read Example ............................................................................................. 122
GPTM Module Block Diagram ........................................................................................ 159
16-Bit Input Edge Count Mode Example .......................................................................... 163
16-Bit Input Edge Time Mode Example ........................................................................... 164
16-Bit PWM Mode Example ............................................................................................ 165
WDT Module Block Diagram .......................................................................................... 194
UART Module Block Diagram ......................................................................................... 218
UART Character Frame ................................................................................................. 219
SSI Module Block Diagram ............................................................................................. 256
TI Synchronous Serial Frame Format (Single Transfer) .................................................... 259
TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 259
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 260
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 260
Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 261
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 262
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 262
Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 263
I
I
START and STOP Conditions ......................................................................................... 294
Complete Data Transfer with a 7-Bit Address ................................................................... 295
R/S Bit in First Byte ........................................................................................................ 295
Data Validity During Bit Transfer on the I
Master Single SEND ...................................................................................................... 298
Master Single RECEIVE ................................................................................................. 299
Master Burst SEND ....................................................................................................... 300
2
2
C Block Diagram ......................................................................................................... 293
C Bus Configuration .................................................................................................... 294
®
300 Series High-Level Block Diagram ................................................................ 23
Preliminary
2
C Bus ............................................................... 295
LM3S300 Microcontroller
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