LM3S300 Luminary Micro, Inc, LM3S300 Datasheet - Page 268

• Manufacturer Part Number: LM3S300
• Description: Lm3s300 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Synchronous Serial Interface (SSI)
SSI Control 0 (SSICR0)
SSI0 base: 0x4000.8000
Offset 0x000
Type R/W, reset 0x0000.0000
268
Bit/Field
31:16
15:8
R/W
RO
7
6
31
15
0
0
R/W
RO
Register 1: SSI Control 0 (SSICR0), offset 0x000
SSICR0 is control register 0 and contains bit fields that control various functions within the SSI
module. Functionality such as protocol mode, clock rate, and data size are configured in this register.
30
14
0
0
R/W
RO
29
13
reserved
0
0
Name
SCR
SPH
SPO
R/W
RO
28
12
0
0
SCR
R/W
RO
27
11
0
0
Type
R/W
R/W
R/W
RO
R/W
RO
26
10
0
0
0x0000
R/W
RO
Reset
25
0x00
0
9
0
0
0
Preliminary
R/W
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Serial Clock Rate
The value SCR is used to generate the transmit and receive bit rate of
the SSI. The bit rate is:
BR=FSSIClk/(CPSDVSR * (1 + SCR))
where CPSDVSR is an even value from 2-254 programmed in the
SSICPSR register, and SCR is a value from 0-255.
SSI Serial Clock Phase
This bit is only applicable to the Freescale SPI Format.
The SPH control bit selects the clock edge that captures data and allows
it to change state. It has the most impact on the first bit transmitted by
either allowing or not allowing a clock transition before the first data
capture edge.
When the SPH bit is 0, data is captured on the first clock edge transition.
If SPH is 1, data is captured on the second clock edge transition.
SSI Serial Clock Polarity
This bit is only applicable to the Freescale SPI Format.
When the SPO bit is 0, it produces a steady state Low value on the
SSIClk pin. If SPO is 1, a steady state High value is placed on the
SSIClk pin when data is not being transferred.
SPH
R/W
RO
23
0
7
0
SPO
R/W
RO
22
0
6
0
R/W
RO
21
0
5
0
FRF
R/W
RO
20
0
4
0
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
DSS
R/W
RO
17
0
1
0
June 04, 2008
R/W
RO
16
0
0
0