LM3S3749 Luminary Micro, Inc, LM3S3749 Datasheet - Page 278

• Manufacturer Part Number: LM3S3749
• Description: Lm3s3749 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
General-Purpose Input/Outputs (GPIOs)
GPIO Digital Enable (GPIODEN)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x51C
Type R/W, reset -
278
Bit/Field
31:8
RO
RO
31
15
0
0
RO
RO
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C
Note:
The GPIODEN register is the digital enable register. By default, with the exception of the GPIO
signals used for JTAG/SWD function, all other GPIO signals are configured out of reset to be undriven
(tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not
allow the pin voltage into the GPIO receiver. To use the pin in a digital function (either GPIO or
alternate function), the corresponding GPIODEN bit must be set.
Note:
30
14
0
0
RO
RO
29
13
reserved
0
0
Name
Pins configured as digital inputs are Schmitt-triggered.
The commit control registers provide a layer of protection against accidental programming
of critical hardware peripherals. Writes to protected bits of the GPIO Alternate Function
Select (GPIOAFSEL) register (see page 269), GPIO Pull-Up Select (GPIOPUR) register
(see page 275), and GPIO Digital Enable (GPIODEN) register (see page 278) are not
committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 280) has been
unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 281)
have been set to 1.
RO
RO
28
12
0
0
reserved
RO
RO
27
11
0
0
Type
RO
RO
RO
26
10
0
0
RO
RO
Reset
25
0x00
0
9
0
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
RO
23
0
7
-
R/W
RO
22
0
6
-
R/W
RO
21
0
5
-
R/W
RO
20
0
4
-
DEN
R/W
RO
19
0
3
-
R/W
RO
18
0
2
-
R/W
RO
17
0
1
June 02, 2008
-
R/W
RO
16
0
0
-