LM3S3749 Luminary Micro, Inc, LM3S3749 Datasheet - Page 556

• Manufacturer Part Number: LM3S3749
• Description: Lm3s3749 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Type
Univeral Serial Bus (USB) Controller
USBTXCSRL1 Host Mode
USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1)
Base 0x4005.0000
Offset 0x112
Type R/W, reset 0x00
556
Host
Device
Bit/Field
NAKTO /
R/W0C
INCTX
7
6
5
4
7
0
CLRDT
W1S
Register 53: USB Transmit Control and Status Endpoint 1 Low (USBTXCSRL1),
offset 0x112
Register 54: USB Transmit Control and Status Endpoint 2 Low (USBTXCSRL2),
offset 0x122
Register 55: USB Transmit Control and Status Endpoint 3 Low (USBTXCSRL3),
offset 0x132
USBTXCSRLn is an 8-bit register that provides control and status bits for transfers through the
currently selected transmit endpoint.
6
0
NAKTO / INCTX
STALLED
R/W0C
STALLED
5
0
CLRDT
SETUP
Name
SETUP
R/W
4
0
FLUSH
W1C
3
0
R/W0C
R/W0C
Type
W1S
R/W
ERROR
R/W0C
2
0
FIFONE
R/W0C
Reset
1
0
0
0
0
0
Preliminary
TXRDY
R/W0C
0
0
Description
NAK Timeout / Incomplete TX
Bulk endpoints only: This bit is set when the transmit endpoint is halted
following the receipt of NAK responses for longer than the time set as
the NAK Limit by the USBTXINTERVALn register. The CPU should
clear this bit to allow the endpoint to continue.
High-bandwidth interrupt endpoints only: This bit is set if no response
is received from the device to which the packet is being sent.
Clear Data Toggle
The CPU writes a 1 to this bit to reset the endpoint data toggle to 0.
Endpoint Stalled
This bit is set when a STALL handshake is received. When this bit is
set, any DMA request that is in progress is stopped, the FIFO is
completely flushed, and the TXRDY bit is cleared. The CPU should clear
this bit.
Setup Packet
The CPU sets this bit, at the same time as the TXRDY bit is set, to send
a SETUP token instead of an OUT token for the transaction.
Note:
Setting this bit also clears DT.
June 02, 2008