LM3S3749 Luminary Micro, Inc, LM3S3749 Datasheet - Page 87

• Manufacturer Part Number: LM3S3749
• Description: Lm3s3749 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

June 02, 2008
Bit/Field
19:17
16:14
13
12
11
PWMDIV
reserved
reserved
BYPASS
PWRDN
Name
Type
R/W
R/W
R/W
RO
RO
Reset
0x7
0
1
1
1
Preliminary
Description
PWM Unit Clock Divisor
This field specifies the binary divisor used to predivide the system clock
down for use as the timing reference for the PWM module. This clock
is only power 2 divide and rising edge is synchronous without phase
shift from the system clock.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PLL Power Down
This bit connects to the PLL PWRDN input. The reset value of 1 powers
down the PLL.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PLL Bypass
Chooses whether the system clock is derived from the PLL output or
the OSC source. If set, the clock that drives the system is the OSC
source. Otherwise, the clock that drives the system is the PLL output
clock divided by the system divider.
Note:
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Divisor
/2
/4
/8
/16
/32
/64
/64
/64 (default)
The ADC must be clocked from the PLL or directly from a
14-MHz to 18-MHz clock source to operate properly. While
the ADC works in a 14-18 MHz range, to maintain a 1 M
sample/second rate, the ADC must be provided a 16-MHz
clock source.
LM3S3749 Microcontroller
87