LM3S3749 Luminary Micro, Inc, LM3S3749 Datasheet - Page 491

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LM3S3749

Manufacturer Part Number
LM3S3749
Description
Lm3s3749 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet

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Reset
Reset
Type
Type
I2C Master Masked Interrupt Status (I2CMMIS)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x018
Type RO, reset 0x0000.0000
June 02, 2008
Bit/Field
31:1
RO
RO
0
31
15
0
0
RO
RO
Register 7: I
This register specifies whether an interrupt was signaled.
30
14
0
0
RO
RO
29
13
reserved
0
0
Name
MIS
RO
RO
28
12
0
0
2
C Master Masked Interrupt Status (I2CMMIS), offset 0x018
RO
RO
27
11
0
0
Type
RO
RO
RO
RO
26
10
0
0
RO
RO
Reset
25
0x00
0
9
0
0
reserved
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Masked Interrupt Status
This bit specifies the raw interrupt state (after masking) of the I
block. If set, an interrupt was signaled; otherwise, an interrupt has not
been generated since the bit was last cleared.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
RO
RO
19
0
3
0
LM3S3749 Microcontroller
RO
RO
18
0
2
0
RO
RO
17
0
1
0
2
MIS
C master
RO
RO
16
0
0
0
491

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