MT16VDDT3264 Micron, MT16VDDT3264 Datasheet - Page 12

• Manufacturer Part Number: MT16VDDT3264
• Description: 184-Pin DDR SDRAM DIMMs (x64)
• Manufacturer: Micron

I
(Notes: 1–5, 8, 10, 12; notes appear following parameter tables)
(0°C ≤ T
*DRAM components only
a - Value calculated as one module bank in this operating condition, and all other banks in I
b - Value calculated reflects all module banks in this operating condition.
32, 64 Meg x 64 DDR SDRAM DIMMs
DD16C32_64X64AG_C.p65 – Rev. C; Pub. 3/02
PARAMETER/CONDITION
OPERATING CURRENT: One device bank; Active-Precharge;
t
inputs changing once per clock cycle; Address and control inputs
changing once every two clock cycles
OPERATING CURRENT: One device bank; Active-Read-Precharge;
Burst = 2;
Address and control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks I
idle; Power-down mode;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
t
changing once per clock cycle. V
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank
active; Power-down mode;
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device I
bank; Active-Precharge;
DM, and DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;
One device bank active; Address and control inputs changing
once per clock cycle;
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once
per clock cycle;
changing twice per clock cycle
AUTO REFRESH CURRENT
SELF REFRESH CURRENT: CKE ≤ 0.2V
allowed;
only during Active, READ, or WRITE commands.
DD
OPERATING CURRENT: Four device bank interleaving
RC =
CK =
READs (BL = 4) with auto precharge,
SPECIFICATIONS AND CONDITIONS
t
t
RC (MIN);
CK (MIN); CKE = HIGH; Address and other control inputs
A
≤ +70°C; V
t
t
CK =
RC =
t
t
t
CK =
t
RC (MIN);
CK (MIN); Address and control inputs change
CK =
DD
t
t
CK =
Q = +2.5V ±0.2V, V
CK (MIN); DQ, DM, and DQS inputs
t
CK (MIN); DQ, DM, and DQS
t
RC =
t
CK =
t
t
CK =
t
CK (MIN); I
CK =
t
RAS (MAX);
t
CK (MIN); CKE = LOW;
t
IN
CK (MIN); I
t
CK (MIN); CKE = LOW
= V
REF
OUT
t
RC = minimum
DD
for DQ, DQS, and DM
= 0mA
t
CK =
= +2.5V ±0.2V)
OUT
= 0mA;
t
t
t
RC =
RC = 15.625µs
CK (MIN); DQ,
*
t
(256MB MODULE)
RFC (MIN)
t
12
RC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
I
I
I
I
I
SYM
DD
184-PIN DDR SDRAM DIMMs
I
I
DD
I
DD
DD
DD
DD
DD
I
I
DD
DD
DD
DD
DD
4W
5A
3N
2P
2F
3P
4R
0
1
5
6
7
b
a
a
b
a
b
b
b
a
b
b
a
-335
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
DD
256MB, 512MB (x64)
2P, power-down mode.
-26A/-265
MAX
3,520
2,624
864
984
720
288
720
904
904
80
32
48
3,280
2,104
-202
824
904
560
288
560
744
744
48
80
48
UNITS NOTES
©2002, Micron Technology, Inc.
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
21, 28,
21, 28,
20, 43
20, 43
20, 43
20, 45
24, 45
20, 44
45
46
45
42
20
9