MT16VDDT3264 Micron, MT16VDDT3264 Datasheet - Page 6

• Manufacturer Part Number: MT16VDDT3264
• Description: 184-Pin DDR SDRAM DIMMs (x64)
• Manufacturer: Micron

GENERAL DESCRIPTION
high-speed CMOS, dynamic random-access, 256MB and
512MB unbuffered memory modules organized in a
x64 configuration. These modules use internally con-
figured quad-bank DDR SDRAM devices.
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-
prefetch architecture with an interface designed to
transfer two data words per clock cycle at the I/O pins.
A single read or write access for the DDR SDRAM mod-
ule effectively consists of a single 2n-bit wide, one-
clock-cycle data transfer at the internal DRAM core and
two corresponding n-bit wide, one-half-clock-cycle
data transfers at the I/O pins.
ternally, along with data, for use in data capture at the
receiver. DQS is an intermittent strobe transmitted by
the DDR SDRAM during READs and by the memory con-
troller during WRITEs. DQS is edge-aligned with data
for READs and center-aligned with data for WRITEs.
differential clock inputs (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to
as the positive edge of CK. Commands (address and
control signals) are registered at every positive edge of
CK. Input data is registered on both edges of DQS, and
output data is referenced to both edges of DQS, as well
as to both edges of CK.
are burst oriented; accesses start at a selected location
and continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the device bank and row to be accessed (BA0,
BA1 select devices bank; A0-A11 select device row for
the 256MB module, A0-A12 select device row for the
512MB module). The address bits registered coinci-
dent with the READ or WRITE command are used to
select the device bank and the starting device column
location for the burst access.
mable READ or WRITE burst lengths of 2, 4, or 8 loca-
tions. An auto precharge function may be enabled to
provide a self-timed row precharge that is initiated at
the end of the burst access.
SDRAM modules allows for concurrent operation,
thereby providing high effective bandwidth by hiding
row precharge and activation time.
32, 64 Meg x 64 DDR SDRAM DIMMs
DD16C32_64X64AG_C.p65 – Rev. C; Pub. 3/02
The MT16VDDT3264A and MT16VDDT6464A are
These DDR SDRAM modules use a double data rate
A bidirectional data strobe (DQS) is transmitted ex-
These DDR SDRAM modules operate from multiple
Read and write accesses to the DDR SDRAM modules
These DDR SDRAM modules provide for program-
The pipelined, multibank architecture of DDR
6
power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All out-
puts are SSTL_2, Class II compatible. For more infor-
mation regarding DDR SDRAM operation, refer to the
128Mb and 256Mb DDR SDRAM data sheets.
SERIAL PRESENCE-DETECT OPERATION
ence-detect (SPD). The SPD function is implemented
using a 2,048-bit EEPROM. This nonvolatile storage de-
vice contains 256 bytes. The first 128 bytes can be
programmed by Micron to identify the module type
and various SDRAM organizations and timing param-
eters. The remaining 128 bytes of storage are available
for use by the customer. System READ/WRITE opera-
tions between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard IIC bus
using the DIMM’s SCL (clock) and SDA (data) signals,
together with SA(2:0), which provide eight unique
DIMM/EEPROM addresses.
REGISTER DEFINITION
MODE REGISTER
of operation of the DDR SDRAM. This definition in-
cludes the selection of a burst length, a burst type, a
CAS latency and an operating mode, as shown in the
Mode Register Diagram. The mode register is pro-
grammed via the MODE REGISTER SET command (with
BA0 = 0 and BA1 = 0) and will retain the stored informa-
tion until it is programmed again or the device loses
power (except for bit A8, which is self-clearing).
contents of the memory, provided it is performed cor-
rectly. The mode register must be loaded (reloaded)
when all device banks are idle and no bursts are in
progress, and the controller must wait the specified
time before initiating the subsequent operation. Vio-
lating either of these requirements will result in un-
specified operation.
specifies the type of burst (sequential or interleaved), A4-
A6 specify the CAS latency, and A7-A11 (for the 256MB
module) or A7-A12 (for the 512MB module) specify the
operating mode.
Burst Length
oriented, with the burst length being programmable, as
shown in Mode Register Diagram. The burst length
determines the maximum number of column locations
An auto refresh mode is provided, along with a
These DDR SDRAM modules incorporate serial pres-
The mode register is used to define the specific mode
Reprogramming the mode register will not alter the
Mode register bits A0-A2 specify the burst length, A3
Read and write accesses to the DDR SDRAM are burst
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM DIMMs
256MB, 512MB (x64)
©2002, Micron Technology, Inc.