MT16VDDT3264 Micron, MT16VDDT3264 Datasheet - Page 3

• Manufacturer Part Number: MT16VDDT3264
• Description: 184-Pin DDR SDRAM DIMMs (x64)
• Manufacturer: Micron

PIN DESCRIPTIONS
NOTE: Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables for pin number and symbol information.
32, 64 Meg x 64 DDR SDRAM DIMMs
DD16C32_64X64AG_C.p65 – Rev. C; Pub. 3/02
16, 17, 75, 76, 137, 138
48, 115 (512MB), 118,
27, 29, 32, 37, 41, 43,
122, 125, 130, 141
PIN NUMBERS
63, 65, 154
157, 158
21, 111
52, 59
91
1
CK1#, CK2, CK2#
CK0, CK0#, CK1,
WE#, CAS#,
CKE0, CKE1
SYMBOL
BA0, BA1
S0#, S1#
A0-A11
A0-A12
256MB
512MB
RAS#
SDA
V
REF
Output
Input/
TYPE
Input
Input
Input
Input
Input
Input
Input
3
SSTL_2 reference voltage.
Command Inputs: RAS#, CAS#, and WE# (along with
S#) define the command being entered.
Clock: CK and CK# are differential clock inputs. All
address and control input signals are sampled on the
crossing of the positive edge of CK and negative
edge of CK#. Output data (DQ and DQS) is refer-
enced to the crossings of CK and CK#.
Clock Enable: CKE HIGH activates and CKE LOW
deactivates the internal clock, input buffers and
output drivers. Taking CKE LOW provides PRECHARGE
POWER-DOWN and SELF REFRESH operations (all
device banks idle), or ACTIVE POWER-DOWN (row
ACTIVE in any device bank). CKE is synchronous for
POWER-DOWN entry and exit, and for SELF REFRESH
entry. CKE is asynchronous for SELF REFRESH exit and
for disabling the outputs. CKE must be maintained
HIGH throughout read and write accesses. Input
buffers (excluding CK, CK#, and CKE) are disabled
during POWER-DOWN. Input buffers (excluding CKE)
are disabled during SELF REFRESH. CKE is an SSTL_2
input but will detect an LVCMOS LOW level after V
is applied.
Chip Select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All com-
mands are masked when S# is registered HIGH. S# is
considered part of the command code.
Bank Address: BA0 and BA1 define to which device
bank an ACTIVE, READ, WRITE, or PRECHARGE
command is being applied.
Address Inputs: A0-A11/A12 provide the row address for
ACTIVE commands, and the column address and auto
precharge bit (A10) for READ/WRITE commands, to select
one location out of the memory array in the respective
device bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to
one device bank (A10 LOW, device bank selected by BA0,
BA1) or all device banks (A10 HIGH). The address
inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which
mode register (mode register or extended mode
register) is loaded during the LOAD MODE REGISTER
command.
Serial Presence-Detect Data: SDA is a bidirectional pin
used to transfer addresses and data into and out of
the presence-detect portion of the module.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM DIMMs
DESCRIPTION
256MB, 512MB (x64)
©2002, Micron Technology, Inc.
DD