MT18VDDT3272 Micron, MT18VDDT3272 Datasheet - Page 10

• Manufacturer Part Number: MT18VDDT3272
• Description: 184-Pin Registered DDR SDRAM DIMMs (x72)
• Manufacturer: Micron

TRUTH TABLE – COMMANDS
(Note: 1)
TRUTH TABLE – DM OPERATION
(Note: 10)
NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.
COMMANDS
of available commands. For a more detailed description
32, 64 Meg x 72 DDR SDRAM DIMMs
DD18C32_64X72AG_B.p65–Rev. B, Pub. 1/02
NAME (FUNCTION)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
NAME (FUNCTION)
WRITE Enable
WRITE Inhibit
The Truth Tables below provides a general reference
10. Used to mask write data; provided coincident with the corresponding data.
2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register;
3. BA0-BA1 provide device bank address and A0-A11 (256MB) or A0-A12 (512MB) provide device row address.
4. BA0-BA1 provide device bank address; A0-A9 provide device column address; A10 HIGH enables the auto precharge
5. A10 LOW: BA0-BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0-
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls device row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for
9. DESELECT and NOP are functionally interchangeable.
BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A11 (for 256MB
module) or A0-A12 (for 512MB module) provide the op-code to be written to the selected mode register.
feature (nonpersistent), and A10 LOW disables the auto precharge feature.
BA1 are “Don’t Care.”
READ bursts with auto precharge enabled and for WRITE bursts.
10
of commands and operations, refer to the 128Mb and
256Mb DDR SDRAM data sheets.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-pin DDR SDRAM DIMMs
CS# RAS# CAS# WE#
H
L
L
L
L
L
L
L
L
256MB, 512MB (ECC x72)
X
H
H
H
H
L
L
L
L
H
H
X
H
H
L
L
L
L
H
H
H
H
X
L
L
L
L
Bank/Row
Bank/Col
Bank/Col
Op-Code
ADDR
Code
DM
X
X
X
X
©2002, Micron Technology, Inc.
H
L
NOTES
Valid
6, 7
DQs
X
9
9
3
4
4
8
5
2