MT18VDDT3272 Micron, MT18VDDT3272 Datasheet - Page 18

• Manufacturer Part Number: MT18VDDT3272
• Description: 184-Pin Registered DDR SDRAM DIMMs (x72)
• Manufacturer: Micron

NOTES (continued)
28. V
29. The clock is allowed up to ±150ps of jitter. Each
30.
31. READs and WRITEs with auto precharge are not
32. Any positive glitch must be less than
33. Normal Output Drive Curves:
32, 64 Meg x 72 DDR SDRAM DIMMs
DD18C32_64X72AG_B.p65–Rev. B, Pub. 1/02
160
140
120
100
80
60
40
20
0
0.0
active while any device bank is active.
timing parameter is allowed to vary by the same
amount.
t
minimum actually applied to the device CK and
CK/ inputs, collectively during bank active.
allowed to be issued until
prior to the internal precharge command being
issued.
cycle and not more than +400mV or 2.9 volts,
whichever is less. Any negative glitch must be less
than
300mV or 2.2 volts, whichever is more positive.
HPmin is the lesser of
DD
must not vary more than 4% if CKE is not
1
/
3
of the clock cycle and not exceed either -
0.5
Pull-Down Characteristics
1.0
Figure A
V
t
CL minimum and
OUT
(V)
t
RASmin can be satisfied
1.5
1
/
3
2.0
of the clock
t
CH
2.5
18
-100
-120
-140
-160
-180
-200
-20
-40
-60
-80
0
a) The full variation in driver pull-down current
b) The variation in driver pull-down current
c) The full variation in driver pull-up current from
d) The variation in driver pull-up current within
e) The full variation in the ratio of the maximum
f) The full variation in the ratio of the nominal
0.0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-pin DDR SDRAM DIMMs
from minimum to maximum process, tempera-
ture and voltage will lie within the outer
bounding lines of the V-I curve of Figure A.
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I curve
of Figure A.
minimum to maximum process, temperature
and voltage will lie within the outer bounding
lines of the V-I curve of Figure B.
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure
B.
to minimum pull-up and pull-down current
should be between .71 and 1.4, for device drain-
to-source voltages from 0.1V to 1.0 Volt, and at
the same voltage and temperature.
pull-up to pull-down current should be unity
±10%, for device drain-to-source voltages from
0.1V to 1.0 volt.
256MB, 512MB (ECC x72)
0.5
Pull-Up Characteristics
Figure B
1.0
V
DD
Q - V
OUT
(V)
1.5
©2002, Micron Technology, Inc.
2.0
2.5