MT28F128J3FS-15F Micron, MT28F128J3FS-15F Datasheet - Page 2
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MT28F128J3FS-15F
Manufacturer Part Number
MT28F128J3FS-15F
Description
128Mb Q-FLASH MEMORY
Manufacturer
Micron
Datasheet
1.MT28F128J3FS-15F.pdf
(51 pages)
GENERAL DESCRIPTION
erasable (Flash), programmable memory containing
134,217,728 bits organized as 16,777,218 bytes (8 bits)
or 8,388,608 words (16 bits). This 128Mb device is orga-
nized as one hundred twenty-eight 128KB erase blocks.
as 8,388,608 bytes (8 bits) or 4,194,304 words (16 bits).
This 64Mb device is organized as sixty-four 128KB erase
blocks.
organized as 4,194,304 bytes (8 bits) or 2,097,152 words
(16 bits). This 32Mb device is organized as thirty-two
128KB erase blocks.
ing. They also have common flash interface (CFI) that
permits software algorithms to be used for entire fami-
lies of devices. The software is device-independent,
JEDEC ID-independent with forward and backward
compatibility.
lows a single, simple software driver in all host systems
to work with all SCS-compliant Flash memory devices.
The SCS provides the fastest system/device data trans-
fer rates and minimizes the device and system-level
implementation costs.
device accommodates V
block erase, program, or lock bit configuration, or
hardwired to V
treated as an input pin to enable erasing, program-
ming, and block locking. When V
V
disabled. Block erase suspend mode enables the user
to stop block erase to read data from or program data to
any other blocks. Similarly, program suspend mode
enables the user to suspend programming to read data
or execute code from any unsuspended blocks.
128Mb, 64Mb, 32Mb Q-Flash Memory
MT28F640J3_6.p65 – Rev. 5, Pub. 6/02
CC
The MT28F128J3 is a nonvolatile, electrically block-
The MT28F640J3 contains 67,108,864 bits organized
Similarly, the MT28F320J3 contains 33,554,432 bits
These three devices feature in-system block lock-
Additionally, the scalable command set (SCS) al-
To optimize the processor-memory interface, the
lockout voltage (V
CC
, depending on the application. V
LKO
PEN
), all program functions are
, which is switchable during
PEN
is lower than the
PEN
is
2
application programming. V
can provide data protection when connected to ground.
This pin also enables program or erase lockout during
power transition.
vidual block locking that can lock and unlock a block
using the sector lock bits command sequence.
block lock feature for additional code security. This
feature provides an OTP function for locking the top
two blocks, the bottom two blocks, or the entire device.
This feature is available only on the MT28F320J3.
additional indicator of the internal state machine (ISM)
activity by providing a hardware signal of both status
and status masking. This status indicator minimizes
central processing unit (CPU) overhead and system
power consumption. In the default mode, STS acts as
an RY/BY# pin. When LOW, STS indicates that the ISM
is performing a block erase, program, or lock bit con-
figuration. When HIGH, STS indicates that the ISM is
ready for a new command.
disabling the device by activating the device’s control
logic, input buffer, decoders, and sense amplifiers.
to the device. BYTE# at logic LOW selects an 8-bit mode
with address A0 selecting between the low byte
and the high byte. BYTE# at logic HIGH enables 16-bit
operation.
disabled and RP# is at V
abled. A reset time (
switches HIGH until outputs are valid. Likewise, the
device has a wake time (
WRITEs to the command user interface (CUI) are rec-
ognized. When RP# is at GND, it provides write protec-
tion, resets the ISM, and clears the status register.
V
Micron’s even-sectored Q-Flash devices offer indi-
The MT28F320J3 also supports the new security
Status (STS) is a logic signal output that gives an
Three chip enable (CE) pins are used for enabling and
BYTE# enables selecting x8 or x16 READs/WRITEs
RP# is used to reset the device. When the device is
PEN
serves as an input with 2.7V, 3.3V, or 5V for
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
t
RWH) is required after RP#
CC
t
RS) from RP# HIGH until
, the standby mode is en-
PEN
in this Q-Flash
PRELIMINARY
©2002, Micron Technology, Inc.
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