IDT72V2101L15PFI IDT, Integrated Device Technology Inc, IDT72V2101L15PFI Datasheet - Page 25
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IDT72V2101L15PFI
Manufacturer Part Number
IDT72V2101L15PFI
Description
IC FIFO SS 131X18 15NS 64QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V2111L15PFGI.pdf
(27 pages)
Specifications of IDT72V2101L15PFI
Function
Synchronous
Memory Size
2.3K (131 x 18)
Data Rate
67MHz
Access Time
15ns
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Configuration
Dual
Density
2.25Mb
Access Time (max)
10ns
Word Size
9b
Organization
256Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.45V
Supply Current
55mA
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V2101L15PFI
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V2101L15PFI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V2101L15PFI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
signals of multiple devices. Status flags can be detected from any one
device. The exceptions are the EF and FF functions in IDT Standard mode
and the IR and OR functions in FWFT mode. Because of variations in skew
between RCLK and WCLK, it is possible for EF/FF deassertion and IR/OR
assertion to vary by one cycle between FIFOs. In IDT Standard mode, such
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
Word width may be increased simply by connecting together the control
GATE
(1)
FIRST WORD FALL THROUGH/
DATA IN
SERIAL INPUT (FWFT/SI)
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FULL FLAG/INPUT READY (FF/IR) #2
FULL FLAG/INPUT READY (FF/IR)
TM
RETRANSMIT (RT)
262,144 x 9, 524,288 x 9
m + n
WRITE CLOCK (WCLK)
PROGRAMMABLE (PAF)
WRITE ENABLE (WEN)
HALF-FULL FLAG (HF)
Figure 19. Block Diagram of 262,144 x 18 and 524,288 x 18 Width Expansion
D
0
- Dm
LOAD (LD)
m
#1
72V2101
72V2111
IDT
FIFO
#1
Dm
m
+1
- Dn
Q
25
0
n
- Qm
problems can be avoided by creating composite flags, that is, ANDing EF of
every FIFO, and separately ANDing FF of every FIFO. In FWFT mode,
composite flags can be created by ORing OR of every FIFO, and separately
ORing IR of every FIFO.
72V2111 devices. D
Q
be attained by adding additional IDT72V2101/72V2111 devices.
0
-Q
Figure 19 demonstrates a width expansion using two IDT72V2101/
72V2101
72V2111
8
FIFO
from each device form an 18-bit wide output bus. Any word width can
IDT
#2
READ CLOCK (RCLK)
n
READ ENABLE (REN)
OUTPUT ENABLE (OE)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
EMPTY FLAG/OUTPUT READY (EF/OR) #1
PROGRAMMABLE (PAE)
0
Qm
- D
+1
8
from each device form an 18-bit wide input bus and
- Qn
COMMERCIAL AND INDUSTRIAL
m + n
TEMPERATURE RANGES
DATA OUT
4669 drw 22
GATE
(1)