IDT72V2101L15PFI IDT, Integrated Device Technology Inc, IDT72V2101L15PFI Datasheet - Page 9
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IDT72V2101L15PFI
Manufacturer Part Number
IDT72V2101L15PFI
Description
IC FIFO SS 131X18 15NS 64QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V2111L15PFGI.pdf
(27 pages)
Specifications of IDT72V2101L15PFI
Function
Synchronous
Memory Size
2.3K (131 x 18)
Data Rate
67MHz
Access Time
15ns
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Configuration
Dual
Density
2.25Mb
Access Time (max)
10ns
Word Size
9b
Organization
256Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.45V
Supply Current
55mA
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V2101L15PFI
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V2101L15PFI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V2101L15PFI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
8
8
8
8
8
8
7
7
7
7
IDT72V2101 (262,144 x 9⎯BIT)
EMPTY OFFSET (MID-BYTE) REGISTER
FULL OFFSET (MID-BYTE) REGISTER
TM
EMPTY OFFSET (LSB) REGISTER
03H if LD is HIGH at Master Reset
00H if LD is LOW at Master Reset
FFH if LD is HIGH at Master Reset
FFH if LD is HIGH at Master Reset
FULL OFFSET (LSB) REGISTER
7FH if LD is LOW at Master Reset
7FH if LD is LOW at Master Reset
262,144 x 9, 524,288 x 9
03H if LD is HIGH at Master Reset
00H if LD is LOW at Master Reset
DEFAULT VALUE
DEFAULT VALUE
DEFAULT VALUE
DEFAULT VALUE
2 1
2 1
Figure 3. Offset Register Location and Default Values
(MSB) REGISTER
(MSB) REGISTER
EMPTY OFFSET
FULL OFFSET
DEFAULT
DEFAULT
0H
0H
0
0
0
0
0
0
9
8
8
8
8
8
8
7
7
7
7
IDT72V2111 (524,288 x 9⎯BIT)
EMPTY OFFSET (MID-BYTE) REGISTER
FULL OFFSET (MID-BYTE) REGISTER
EMPTY OFFSET (LSB) REGISTER
FULL OFFSET (LSB) REGISTER
FFH if LD is HIGH at Master Reset
7FH if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
00H if LD is LOW at Master Reset
FFH if LD is HIGH at Master Reset
03H if LD is HIGH at Master Reset
7FH if LD is LOW at Master Reset
00H if LD is LOW at Master Reset
DEFAULT VALUE
DEFAULT VALUE
DEFAULT VALUE
DEFAULT VALUE
COMMERCIAL AND INDUSTRIAL
3
3
2
2
TEMPERATURE RANGES
(MSB) REGISTER
(MSB) REGISTER
EMPTY OFFSET
FULL OFFSET
DEFAULT
DEFAULT
0H
0H
4669 drw 06
0
0
0
0
0
0