IDT72V2111L10PFG8 IDT, Integrated Device Technology Inc, IDT72V2111L10PFG8 Datasheet - Page 10
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IDT72V2111L10PFG8
Manufacturer Part Number
IDT72V2111L10PFG8
Description
IC FIFO SS 512X9 10NS 64QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V2111L15PFGI.pdf
(27 pages)
Specifications of IDT72V2111L10PFG8
Function
Synchronous
Memory Size
4.6K (512 x 9)
Access Time
10ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Rate
-
Other names
72V2111L10PFG8
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V2111L10PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
TM
LD
0
0
0
X
1
1
1
262,144 x 9, 524,288 x 9
WEN
X
0
1
1
1
0
1
REN
X
1
0
1
1
0
1
Figure 4. Programmable Flag Offset Programming Sequence
SEN
1
1
X
X
X
1
0
WCLK
X
X
X
X
RCLK
10
X
X
X
X
X
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (Mid-Byte)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (Mid-Byte)
Full Offset (MSB)
Serial shift into registers:
36 bits for the 72V2101
38 bits for the 72V2111
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with FUll Offset (MSB)
No Operation
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (Mid-Byte)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (Mid-Byte)
Full Offset (MSB)
Write Memory
Read Memory
No Operation
IDT72V2101
IDT72V2111
COMMERCIAL AND INDUSTRIAL
4669 drw 07
TEMPERATURE RANGES