IDT72V2111L10PFG8 IDT, Integrated Device Technology Inc, IDT72V2111L10PFG8 Datasheet - Page 7

• Manufacturer Part Number: IDT72V2111L10PFG8
• Description: IC FIFO SS 512X9 10NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V2111L10PFG8

• Function: Synchronous
• Memory Size: 4.6K (512 x 9)
• Access Time: 10ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Rate: -
• Other names: 72V2111L10PFG8

FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
IDT Standard mode or First Word Fall Through (FWFT) mode. The selection
of which mode will operate is determined during Master Reset, by the state of
the FWFT/SI input.
will be selected. This mode uses the Empty Flag (EF) to indicate whether or
not there are any words present in the FIFO. It also uses the Full Flag function
(FF) to indicate whether or not the FIFO has any free space for writing. In IDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (REN) and RCLK.
be selected. This mode uses Output Ready (OR) to indicate whether or not
there is valid data at the data outputs (Q
indicate whether or not the FIFO has any free space for writing. In the FWFT
mode, the first word written to an empty FIFO goes directly to Q
RCLK rising edges, REN = LOW is not necessary. Subsequent words must
be accessed using the Read Enable (REN) and RCLK.
pending on which timing mode is in effect.
IDT STANDARD MODE
manner outlined in Table 1. To write data into to the FIFO, Write Enable (WEN)
must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (EF) will go HIGH. Subsequent writes will continue
to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH
after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The default setting for this value is stated in the footnote of Table 1. This
parameter is also user programmable. See section on Programmable Flag
Offset Loading.
operations were taking place, the Half-Full flag (HF) would toggle to LOW
once the 131,073th word for IDT72V2101 and 262,145th word for
IDT72V2111 respectively was written into the FIFO. Continuing to write
data into the FIFO will cause the Programmable Almost-Full flag (PAF) to
go LOW. Again, if no reads are performed, the PAF will go LOW after
(262,144-m) writes for the IDT72V2101 and (524,288-m) writes for the
IDT72V2111. The offset “m” is the full offset value. The default setting for
this value is stated in the footnote of Table 1. This parameter is also user
programmable. See section on Programmable Flag Offset Loading.
write operations. If no reads are performed after a reset, FF will go LOW
after D writes to the FIFO. D = 262,144 writes for the IDT72V2101 and 524,288
for the IDT72V2111, respectively.
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
Various signals, both input and output signals operate differently de-
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
If one continued to write data into the FIFO, and we assumed no read
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further
The IDT72V2101/72V2111 support two different timing modes of operation:
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will
TM
262,144 x 9, 524,288 x 9
n)
. It also uses Input Ready (IR) to
n
after three
7
Subsequent read operations will cause PAF and HF to go HIGH at the conditions
described in Table 1. If further read operations occur, without write operations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offset value. Continuing read operations will cause the FIFO to become empty.
When the last word has been read from the FIFO, the EF will go LOW inhibiting
further read operations. REN is ignored when the FIFO is empty.
register-buffered outputs.
7, 8 and 11.
FIRST WORD FALL THROUGH MODE (FWFT)
manner outlined in Table 2. To write data into to the FIFO, WEN must be
LOW. Data presented to the DATA IN lines will be clocked into the FIFO on
subsequent transitions of WCLK. After the first write is performed, the
Output Ready (OR) flag will go LOW. Subsequent writes will continue to fill
up the FIFO. PAE will go HIGH after n + 2 words have been loaded into the
FIFO, where n is the empty offset value. The default setting for this value
is stated in the footnote of Table 2. This parameter is also user program-
mable. See section on Programmable Flag Offset Loading.
operations were taking place, the HF would toggle to LOW once the
131,074th word for the IDT72V2101 and 262,146th word for the IDT72V2111,
respectively was written into the FIFO. Continuing to write data into the
FIFO will cause the PAF to go LOW. Again, if no reads are performed, the
PAF will go LOW after (262,145-m) writes for the IDT72V2101 and
(524,289-m) writes for the IDT72V2111, where m is the full offset value. The
default setting for this value is stated in the footnote of Table 2.
further write operations. If no reads are performed after a reset, IR will go HIGH
after D writes to the FIFO. D = 262,145 writes for the IDT72V2101 and 524,289
writes for the IDT72V2111, respectively. Note that the additional word in FWFT
mode is due to the capacity of the memory plus output register.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 2. If further read operations occur, without
write operations, the PAE will go LOW when there are n + 1 words in the
FIFO, where n is the empty offset value. Continuing read operations will
cause the FIFO to become empty. When the last word has been read from
the FIFO, OR will go HIGH inhibiting further read operations. REN is ignored
when the FIFO is empty.
buffered, and the IR flag output is double register-buffered.
and 12.
If the FIFO is full, the first read operation will cause FF to go HIGH.
When configured in IDT Standard mode, the EF and FF outputs are double
Relevant timing diagrams for IDT Standard mode can be found in Figure
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
If one continued to write data into the FIFO, and we assumed no read
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting
If the FIFO is full, the first read operation will cause the IR flag to go LOW.
When configured in FWFT mode, the OR flag output is triple register-
Relevant timing diagrams for FWFT mode can be found in Figure 9, 10
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES