MT9074AL Zarlink Semiconductor, Inc., MT9074AL Datasheet - Page 14

• Manufacturer Part Number: MT9074AL
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Zarlink Semiconductor, Inc.

Data Sheet
Phase Lock Loop (PLL)
The MT9074 contains a PLL, which can be locked to
either an input 4.096 Mhz clock or the extracted line
clock.The PLL will attenuate jitter from less than
2.5 Hz and roll-off at a rate of 20 dB/decade. Its
intrinsic jitter is less than 0.02 UI. The PLL will meet
the jitter transfer characteristics as specified by ATT
document
recommendations as shown in Figure 11.
Clock Jitter Attenuation Modes
MT9074 has three basic jitter attenuation modes of
operation, selected by the BS/LS and S/FR control
pins. Referring to the mode names given in Table 5
the basic operation of the jitter attenuation modes
are:
•
•
•
In System Bus Synchronous mode pins C4b and F0b
are always configured as inputs, while in the Line
Synchronous and Free-Run modes C4b and F0b are
configured as outputs.
In System Bus Synchronous mode an external clock
is applied to C4b. The applied clock is dejittered by
the internal PLL before being used to synchronize
System Bus Synchronous Mode
Line Synchronous Mode
Free-Run Mode
-0.5
19.5
dB
0
TR
10
62411
and
Figure 11- TR 62411 Jitter Attenuation Curve
the
relevant
Frequency (Hz)
40
the transmitted data. The clock extracted (with no
jitter attenuation performed) from the receive data
can be monitored on pin E1.5o.
In Line Synchronous mode, the clock extracted from
the receive data is dejittered using the internal PLL
and then output on pin C4b. Pin E1.5o provides the
extracted receive clock before it has been dejittered.
The transmit data is synchronous to the clean
receive clock.
In Free-Run mode the transmit data is synchronized
to the internally generated clock. The internal clock
is output on pin C4b. The clock signal extracted from
the receive data is not dejittered and is output
directly on E1.5o.
Depending on the mode selection above, the PLL
can either attenuate transmit clock jitter or the
receive clock jitter. Table 5 shows the appropriate
configuration of each control pin to achieve the
Line Synchronous
Table 5 - Selection of clock jitter attenuation
Synchronous
Mode Name
System Bus
Free-Run
modes using the M/S and MS/FR pins
400
-20 dB/decade
BS/LS
0
1
x
S/FR
1
1
0
PLL locked to E1.5o.
PLL locked to C4b.
PLL free - running.
10K
MT9074
Note
14