MT9074AL Zarlink Semiconductor, Inc., MT9074AL Datasheet - Page 34

• Manufacturer Part Number: MT9074AL
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Zarlink Semiconductor, Inc.

MT9074
34
4) The transmit RAI bit will be one until basic frame
alignment is established, then it will be zero.
5) E-bits can be optionally set to zero until the
equipment interworking relationship is established.
When this has been determined one of the following
will take place:
a) CRC-to-non-CRC operation - E-bits = 0,
b) CRC-to-CRC operation - E-bits as per G.704 and
I.431.
6) All manual re-frames and new basic frame
alignment searches start after the current frame
alignment signal position.
7) After basic frame alignment has been achieved,
loss of frame alignment will occur any time three
consecutive incorrect basic frame alignment signals
are received. Loss of basic frame alignment will
reset the complete framing algorithm.
8) When CRC-4 multiframing has been achieved, the
primary
multiframe alignment will be adjusted to the basic
frame
synchronization. Therefore, the primary basic frame
alignment will not be updated during the CRC-4
multiframing search, but will be updated when the
CRC-4 multiframing search is complete.
Reframe
E1 Mode
The MT9074 will automatically force a reframe, if
three consecutive frame alignment patterns or three
consecutive non-frame alignment bits are in error.
T1 Mode
The MT9074 will automatically force a reframe if the
framing bit error density exceeds the threshold
programmed by control bits RS1-0 (Framing Mode
Select Word page 1H, address 10H). RS1 = RS0 = 0
forces a reframe for 2 errors out of a sliding window
of 4 framing bits. RS1 = 0, RS0 = 1 forces a reframe
with 2 errors out of 5. RS1 = 1, RS0 = 0 forces a
reframe with 2 errors out of 6. RS1 = RS0 = 1
disables the automatic reframe.
In ESF mode, all framing bits are checked. In D4
mode either Ft bits only (if control bit 2 - FSI - of
Framing Mode Select Register is set low) or Ft and
Fs bits are checked (FSI set high). If the D4
secondary yellow alarm is enabled (control bit 1 -
D4SECY of Transmit Alarm Control Word page 1H,
alignment
basic
frame
determined
alignment
during
and
resulting
CRC-4
address 11H) then the Fs bit of frame 12 is not
verified for the loss of frame circuit.
In E1 or T1 mode, receive transparent mode
(selected when bit 3 page 1 address 12H is high) no
reframing is forced by the device.
The user may initiate a software reframe at any time
by setting bit 1, page 1, address 10H high (ReFR).
Once the circuit has commenced reframing the
signaling
synchronization has been achieved.
MT9074 Channel Signaling
Channel Signaling in T1 Mode
In T1 mode, when control bit RBEn (page 1H,
address 14H) is low the MT9074 will insert ABCD or
AB signaling bits into bit 8 of every transmit DS0
channel every 6th frame. The AB or ABCD signaling
bits from received frames 6 and 12 (AB) or from
frames 6, 12, 18 and 24 (ABCD) will be loaded into
an internal storage ram. The transmit AB/ ABCD
signaling nibbles can be passed either via the micro-
ports (for channels with bit 1 set high in the Per Time
Slot Control Word - pages 7H and 8H) or through
related channels of the CSTi serial links, see “Table
6 - STBUS vs. DS1 to Channel Relationship(T1)” on
page 15. The receive signaling bits are always
mapped to the equivalent ST-BUS channels on
CSTo. Memory pages five and six contain the
transmit AB or ABCD nibbles and pages eight and
nine the receive AB or ABCD nibbles for micro-port
CAS access.
The serial control streams that contain the transmit /
receive signaling information (CSTi and CSTo
respectively) are clocked at 2.048 Mhz. The number
of signaling bits to be transmit / received = 24
(timeslots) x 4 bits per timeslot (ABCD) = 24 nibbles.
This leaves many unused nibble positions in the
2.048 Mhz CSTi / CSTo bandwidth. These unused
nibble locations are tristated. The usage of the bit
stream is as follows: the signaling bits are inserted /
reported in the same CSTi / CSTo channels that
correspond to the DS1 channels used in DSTi / DSTo
- see Table , “Table 6 - STBUS vs. DS1 to Channel
Relationship(T1),” on page 15. The control bit MSN
(Signaling Control Word, page 01H, address 14H)
allows for the ABCD bit to use the most significant
nibble of CSTi / CSTo (MSN set high) or the least
significant nibble (MSN set low). Unused nibbles and
timeslots
multiplexing on the CSTo control stream, an
additional control bit CSToEn (Signaling Control
Word, page 01H, address 14H) will tristate the whole
are
bits
tristate.
are
frozen
In
order
until
Data Sheet
to
multiframe
facilitate